On 4/20/21 6:06 PM, Aleksandar Rikalo wrote:
> Hi Philippe,
>
>> The plan is to drop the nanoMIPS disassembler because it is broken
>> since more than 2 years and nobody ever cared to fix it after
>> Stefan's attempt in Nov 2018:
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg576504.ht
From: Petar Jovanovic
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.
Signed-off-by: Petar Jovanovic
---
v2:
- add check_cp1_registers
-Original Message-
From: Leon Alrae [mailto:leon.al...@imgtec.com]
Sent: Tuesday, August 25, 2015 7:58 PM
To: Petar Jovanovic ; qemu-devel@nongnu.org
Cc: petar.jovano...@imgtec.com; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH] target-mips: remove wrong checks for
recip.fmt and
From: Petar Jovanovic
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.
Signed-off-by: Petar Jovanovic
---
target-mips/translate.c |4
of illegal instructions.
Regards,
Petar
From: Daniel Sanders [mailto:daniel.sand...@imgtec.com]
Sent: Monday, December 15, 2014 3:03 PM
To: Vasileios Kalintiris; Petar Jovanovic
Cc: qemu-devel@nongnu.org; Leon Alrae
Subject: RE: [PATCH] target-mips: add CPU definition for MIPS-II
Hi,
FWIW, the
Adding (another) generic model for an old ISA revision is rather
discouraged in QEMU trunk. Can you add a particular real CPU model?
Regards,
Petar
From: Vasileios Kalintiris
Sent: 25 November 2014 11:04
To: address@hidden
Cc: Leon Alrae; address@
er [afaer...@suse.de]
Sent: Wednesday, June 18, 2014 5:21 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: r...@twiddle.net; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [v4 PATCH] target-mips: implement UserLocal Register
Am 29.05.2014 19:36, schrieb Petar Jovanovic:
> From: P
Hi Leon,
thanks for spotting that. Done in v5.
Regards,
Petar
From: Leon Alrae
Sent: Wednesday, June 18, 2014 4:53 PM
To: Petar Jovanovic; Aurelien Jarno; Petar Jovanovic
Cc: r...@twiddle.net; qemu-devel@nongnu.org; afaer...@suse.de
Subject: Re: [Qemu
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
ping
http://patchwork.ozlabs.org/patch/353815/
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Friday, May 30, 2014 10:02 AM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; afaer...@suse.de; r...@twiddle.net
Subject: Re: [v4 PATCH] target
rel32.net]
Sent: Thursday, May 29, 2014 4:26 PM
To: Peter Maydell
Cc: Petar Jovanovic; r...@twiddle.net; Petar Jovanovic; afaer...@suse.de;
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [v3 PATCH] target-mips: implement UserLocal Register
On Thu, May 29, 2014 at 04:06:56PM +0200, Aurelien Jarno wr
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
the translator.
[1] http://patchwork.ozlabs.org/patch/349709/
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Thursday, May 29, 2014 3:08 PM
To: Petar Jovanovic
Cc: Petar Jovanovic; qemu-devel@nongnu.org; afaer...@suse.de; r...@twiddle.net
Subject: Re: [v3
de
> generated with it being true or being false.
Initial version of this patch did not have this flag, but it was added
as requested in code review.
What do you suggest?
From: Aurelien Jarno [aurel...@aurel32.net]
Sent: Thursday, May 29, 2014 2:49 PM
To: Petar
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
st add fields here. When loading you'll need to check the
> version you're loading for whether or not to load the field, and for
> saving you need to increment the version.
Fixed in v3, thanks.
Regards,
Petar
________
From: Andreas Färber [afaer...
son
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 7:20 PM
To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; James Hogan
Subject: Re: [v2 PATCH] target-mips: implement UserLocal Register
On 05/27/2014 09:46 AM, Petar Jovanovic wrote:
> Can you please add more th
tent of HWrena.
P.
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 4:38 AM
To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; James Hogan
Subject:
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 3:35 AM
To: Petar Jovanovic; Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; James Hogan
Subject: Re: [v2 PATCH
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Tuesday, May 27, 2014 12:53 AM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; James Hogan
Subject: Re: [v2 PATCH
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
From: James Hogan [ja...@albanarts.com] on behalf of James Hogan
Sent: Thursday, May 22, 2014 2:19 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement
From: James Hogan [ja...@albanarts.com]
Sent: Thursday, May 22, 2014 2:03 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register
> I think
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Saturday, May 17, 2014 8:11 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2
From: Petar Jovanovic
Add CPUMIPSState in gen_mfc0/mtc0/dmfc0/dmtc0, as it will be used in the
next patch that implements UserLocal register and access to it.
Signed-off-by: Petar Jovanovic
---
target-mips/translate.c | 44
1 file changed, 24
This is a small series of two patches. One expands the number of arguments
for gen_mfc0(), gen_mtc0(), gen_dmfc0(), and gen_dmtc0(), and the second
patch actually implements the register and access to it.
Regards,
Petar
Petar Jovanovic (2):
target-mips: pass CPUMIPSState to gen_mfc0/mtc0/dmfc0
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This regis
From: Andreas Färber [afaer...@suse.de]
Sent: Monday, May 05, 2014 11:55 AM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: riku.voi...@linaro.org; Petar Jovanovic
Subject: Re: [Qemu-devel] [PATCH] linux-user: fix getrusage and wait4 failures
with invalid
ping
http://patchwork.ozlabs.org/patch/337703/
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Tuesday, April 08, 2014 7:24 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; riku.voi...@linaro.org
Subject: [PATCH] linux-user: fix getrusage and
From: Petar Jovanovic
Implementations of system calls getrusage and wait4 have not previously
handled correctly cases when incorrect address of struct rusage is
passed.
This change makes sure return values are correctly set for these cases.
Signed-off-by: Petar Jovanovic
---
linux-user
From: Petar Jovanovic
Flags NONBLOCK and CLOEXEC can have different values on the host and the
guest, so set correct host values before calling accept4().
This fixes several issues with accept4 system call and user-mode of QEMU.
Signed-off-by: Petar Jovanovic
---
v2:
- use
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, March 31, 2014 5:19 PM
To: Petar Jovanovic
Cc: QEMU Developers; Riku Voipio; Petar Jovanovic
Subject: Re: [Qemu-devel] [PATCH] linux-user: pass correct host flags to
accept4()
On 31 March 2014
From: Petar Jovanovic
Flags NONBLOCK and CLOEXEC can have different values on the host and the
guest, so set correct host values before calling accept4().
This fixes several issues with accept4 system call and user-mode of QEMU.
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 13
From: Petar Jovanovic
Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.
Signed-off-by: Matthew Fortune
Signed
: Michael Roth
Cc: qemu-devel@nongnu.org; qemu-sta...@nongnu.org; Petar Jovanovic
Subject: Re: [Qemu-devel] Patch Round-up for stable 1.7.1, freeze on 2013-02-27
On 02/21/14 09:16, Michael Roth wrote:
> Hi everyone,
>
> The following new patches are queued for QEMU stable v1.7.1:
>
> htt
From: Petar Jovanovic
On success, sigtimedwait() returns a signal number that needs to be
translated from a host value to a target value.
This change also fixes issues with sigwait (that is implemented using
sigtimedwait()).
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 16
gards,
Petar
From: Andreas Färber [afaer...@suse.de]
Sent: Friday, February 28, 2014 4:30 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: riku.voi...@linaro.org; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH] linux-user: correct handling of break
exception
From: Petar Jovanovic
Exception with break instruction has not been correctly propagated as
SIGTRAP. This resolves crash issues with examples that use break
instruction on MIPS.
Signed-off-by: Petar Jovanovic
---
linux-user/main.c |4
1 file changed, 4 insertions(+)
diff --git a
From: Andreas Färber [afaer...@suse.de]
Sent: Thursday, February 13, 2014 5:11 PM
To: Peter Maydell; Petar Jovanovic
Cc: QEMU Developers; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
me
only. Sorry!
> You probably wanted to say:
> git://github.com/petar-jovanovic/qemu.git mips-ufrp
I should have written that, yes.
Thanks.
Regards,
Petar
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Thursday, February 13, 2014 3:59 PM
T
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
p
for you to fetch changes up to 736d120af4bf5f3e13b2f90c464b3a24847f78f0:
target-mips: add user-mode FR switch support for MIPS32r5 (2014-02-10
16:46:38 +0100)
--------
Petar Jovanovic (4):
target-mips: add CPU definition fo
From: Petar Jovanovic
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic
Reviewed-by: Eric Johnson
---
target-mips/cpu.h|3 +++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 15
014 2:51 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
> From: Petar Jovanovic
>
> Add mips32r5-generic among CPU
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
From: Petar Jovanovic
Sent: Tuesday, February 04, 2014 2:59 PM
To: Petar Jovanovic
ping
From: Stefan Hajnoczi [stefa...@gmail.com]
Sent: Wednesday, January 08, 2014 5:52 AM
To: Petar Jovanovic
Cc: qemu-stable [qemu-sta...@nongnu.org]; qemu-devel@nongnu.org; Michael Roth
Subject: Re: [Qemu-devel] backport three changes for v1.7.1
On Wed
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 14
From: Petar Jovanovic
Add CP0_Config4, define rw_bitmask.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h|3 +++
target-mips/helper.h |1 +
target-mips/op_helper.c |6 ++
target-mips/translate.c | 15 +--
target-mips
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
Version 2 of the patch series to add mips32r5-generic model with UFR feature.
It includes extra patch to add support for Config4.
Petar Jovanovic (4):
target-mips: add CPU definition for MIPS32R5
target-mips: add support for CP0_Config4
target-mips: add support for CP0_Config5
target
From: Petar Jovanovic
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR
From: Petar Jovanovic
Add CP0_Config5, define rw_bitmask and enable modifications.
Signed-off-by: Petar Jovanovic
---
target-mips/cpu.h| 10 ++
target-mips/helper.h |1 +
target-mips/op_helper.c |5 +
target-mips/translate.c | 16
From: Petar Jovanovic
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions
ping
+cc: qemu-devel@nongnu.org
From: Petar Jovanovic
Sent: Tuesday, December 10, 2013 10:32 AM
To: qemu-stable [qemu-sta...@nongnu.org]
Subject: backport three changes for v1.7.1
Can someone cherry-pick these three changes and put it into the 1.7 stable
ping
http://patchwork.ozlabs.org/patch/295442/
From: Andreas Färber [afaer...@suse.de]
Sent: Friday, November 29, 2013 6:04 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; qemu-stable
Subject: Re: [Qemu-devel
From: Petar Jovanovic
FR bit should be initialized to 1 for MIPS64, under condition that this
bit is writable and that CPU has an FPU unit. It should be initialized to
zero for MIPS32.
This fixes different MIPS32 issues with FPU instructions whose behaviour
defaulted to 64-bit FPU mode.
Signed
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
Can we get these two changes in 1.7?
It has been reviewed and waiting for someone who has commits rights for two
months now.
Regards,
Petar
From: Petar Jovanovic
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
From: Petar Jovanovic
Sent: Tuesday, November 12, 2013 4:40 PM
To: qemu-devel@nongnu.org; riku.voi...@linaro.org
Cc: Petar Jovanovic; peter.mayd...@linaro.org; aurel
ping
http://patchwork.ozlabs.org/patch/287211/
http://patchwork.ozlabs.org/patch/287213/
Riku?
Regards,
Petar
From: Alex Bennée [alex.ben...@linaro.org]
Sent: Tuesday, November 05, 2013 3:46 PM
To: Petar Jovanovic
Cc: Petar Jovanovic; qemu-devel@nongnu.org; peter.mayd...@linaro.org;
riku.voi...@linaro.org; aurel...@aurel32.net; afaer...@suse.de
Subject: Re: [Qemu
Can you please provide full reproduction steps rather than just an
assembly snippet?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1248168
Title:
MIPS, self-modifying code and uncached memory
Stat
From: Alex Bennée [alex.ben...@linaro.org]
Sent: Monday, November 04, 2013 5:46 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; riku.voi...@linaro.org;
Petar Jovanovic; aurel...@aurel32.net; afaer...@suse.de
Subject: Re: [Qemu
From: Petar Jovanovic
Fix shmctl issue by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 4f9c558..abaffde 100644
From: Petar Jovanovic
Creating target_structs header in linux-user/$arch/ and making
target_ipc_perm and target_shmid_ds its first inhabitants.
The struct defintions may/should be further fine-tuned by arch maintainers.
Signed-off-by: Petar Jovanovic
---
v3:
- add GNU licence to the new header
Ping
http://patchwork.ozlabs.org/patch/281527/
From: Petar Jovanovic
Sent: Tuesday, October 22, 2013 5:13 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; riku.voi...@linaro.org; peter.mayd...@linaro.org
Subject: RE: [PATCH] linux
Ping
http://patchwork.ozlabs.org/patch/281527/
From: Petar Jovanovic
Sent: Tuesday, October 15, 2013 2:44 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; riku.voi...@linaro.org; peter.mayd...@linaro.org
Subject: RE: [PATCH] linux
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, October 21, 2013 3:26 PM
To: Petar Jovanovic
Cc: Michael Tokarev; Petar Jovanovic; QEMU Trivial; Riku Voipio; QEMU Developers
Subject: Re: [Qemu-trivial] [Qemu-devel] [PATCH] linux-user: pass
From: Michael Tokarev [m...@tls.msk.ru]
Sent: Monday, October 21, 2013 10:45 AM
To: Petar Jovanovic
Cc: Peter Maydell; Petar Jovanovic; QEMU Trivial; Riku Voipio; QEMU Developers
Subject: Re: [Qemu-trivial] [Qemu-devel] [PATCH] linux-user: pass correct
Ping
http://patchwork.ozlabs.org/patch/281527/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Tuesday, October 08, 2013 7:32 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net; riku.voi...@linaro.org;
peter.mayd
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Friday, October 11, 2013 9:10 PM
To: Petar Jovanovic
Cc: QEMU Developers; QEMU Trivial; Riku Voipio; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH] linux-user: pass correct parameter
From: Petar Jovanovic
Fix shmctl issue by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 4a14a43..1f6492e 100644
From: Petar Jovanovic
Creating target_structs header in linux-user/$arch/ and making
target_ipc_perm and target_shmid_ds its first inhabitants.
The struct defintions may/should be further fine-tuned by arch maintainers.
Signed-off-by: Petar Jovanovic
---
As suggested, this header can be used
This is a known issue.
There was a fix proposal by Thomas Schwinge back in June
http://patchwork.ozlabs.org/patch/250161/
but he has not updated the patch per suggestion ever since, though the patch
as is was much closer to correct behaviour than what it is now in the source.
If anyone is in hur
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Monday, October 07, 2013 6:08 PM
To: Petar Jovanovic
Cc: QEMU Developers; Riku Voipio; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH] linux-user: define ipc_perm and shmid_ds per
arch
From: Petar Jovanovic
Structs ipc_perm and shmid_ds are specific for each architecture and should
be defined accordingly. This change does that, and it also fix shmctl issue
by passing correct parameter buf to do_shmctl().
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 78
ping
http://patchwork.ozlabs.org/patch/274816/
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Friday, September 13, 2013 7:36 PM
To: Petar Jovanovic
Cc: QEMU Developers; Riku Voipio; Petar Jovanovic; Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH
From: Petar Jovanovic
Previous implementation does not take into account that SOL_SOCKET constant
can be arch specific. This change fixes some issues with sendmsg/recvmsg.
Signed-off-by: Petar Jovanovic
---
linux-user/syscall.c | 18 +-
1 file changed, 13 insertions(+), 5
From: Petar Jovanovic
Five tests files for DSP instructions had wrong expected values in the tests.
This change fixes this, and this has been cross-checked by running the same
test binaries on Malta 74K board.
Signed-off-by: Petar Jovanovic
---
tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c
From: Petar Jovanovic
Multiplication of two fractional word elements is not correct when sign
extension/promotion is needed. This change fixes it by adding correct
casts from unsigned to signed values.
In addition, the tests (dpaq_sa_l_w.c and dpsq_sa_l_w.c) have been extended
to trigger the
Will there be an update to this patch?
It would be nice to see this in for 1.6.
As of fp64 mode for o32/Rev2, it does not have to be resolved now.
Regards,
Petar
On Sun, 9 Jun 2013, Thomas Schwinge wrote:
> In my reading of the relevant documents, the latter change is not correct
> for o32, and
ping
Can somebody submit these for 1.6?
Thank you.
Regards,
Petar
From: Petar Jovanovic
Sent: Monday, July 22, 2013 10:52 AM
To: Richard Henderson
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [Qemu-devel] [PATCH] target
ping
Can somebody submit these for 1.6?
Thank you.
Regards,
Petar
__
From: Petar Jovanovic
Sent: Monday, July 22, 2013 10:51 AM
To: Richard Henderson; Petar Jovanovic
Cc: qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [PATCH v2] target-mips: fix
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Tuesday, July 23, 2013 7:33 PM
To: Michael Tokarev
Cc: Petar Jovanovic; qemu-triv...@nongnu.org; riku.voi...@linaro.org;
qemu-devel@nongnu.org; Petar Jovanovic
Subject: Re: [Qemu-devel] [Qemu-trivial
From: Petar Jovanovic
sys_mremap missed 5th argument (new_address), which caused examples that
remap to a specific address to fail.
sys_splice missed 5th and 6th argument which caused different examples to
fail.
This change has an effect on MIPS target only.
Signed-off-by: Petar Jovanovic
ping
From: Petar Jovanovic
Sent: Monday, July 15, 2013 1:46 PM
To: Richard Henderson
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [Qemu-devel] [PATCH] target-mips: fix multiplication in
mipsdsp_rndq15_mul_q15_q15
ping
ping
From: Petar Jovanovic
Sent: Monday, July 15, 2013 1:46 PM
To: Richard Henderson; Petar Jovanovic
Cc: qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [PATCH v2] target-mips: fix mipsdsp_trunc16_sat16_round
ping
From: Petar Jovanovic
sys_futex has 6 arguments, and all of these need to be copied. Fix incorrect
declaration in the mips_syscall_args array.
This change fixes the cases where the 5th and 6th arguments have non-zero
value and have importance. An example is a Linux implementation of
ping
From: Petar Jovanovic
Sent: Monday, July 08, 2013 11:20 AM
To: Richard Henderson
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [Qemu-devel] [PATCH] target-mips: fix multiplication in
mipsdsp_rndq15_mul_q15_q15
ping
ping
From: Petar Jovanovic
Sent: Monday, July 08, 2013 11:14 AM
To: Richard Henderson; Petar Jovanovic
Cc: qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: RE: [PATCH v2] target-mips: fix mipsdsp_trunc16_sat16_round
ping
http://patchwork.ozlabs.org
ping
http://patchwork.ozlabs.org/patch/245990/
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Thursday, June 27, 2013 8:26 PM
To: Petar Jovanovic
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel
ping
http://patchwork.ozlabs.org/patch/255967/
From: Richard Henderson [rth7...@gmail.com] on behalf of Richard Henderson
[r...@twiddle.net]
Sent: Monday, July 01, 2013 4:52 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; aurel
ping
http://patchwork.ozlabs.org/patch/255998/
Riku, can you integrate this change?
Thank you.
Petar
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Tuesday, July 02, 2013 3:44 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; aurel
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Tuesday, July 02, 2013 6:34 PM
To: Petar Jovanovic
Cc: Petar Jovanovic; qemu-devel@nongnu.org; aurel...@aurel32.net;
riku.voi...@linaro.org; r...@twiddle.net
Subject: Re: [PATCH v3] linux-user: improve
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Tuesday, July 02, 2013 3:44 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; Petar Jovanovic; aurel...@aurel32.net;
riku.voi...@linaro.org; r...@twiddle.net
Subject: Re: [PATCH v3] linux-user: improve
From: Peter Maydell [peter.mayd...@linaro.org]
Sent: Thursday, June 27, 2013 7:21 PM
To: Petar Jovanovic
Cc: qemu-devel@nongnu.org; blauwir...@gmail.com; riku.voi...@linaro.org; Petar
Jovanovic; aurel...@aurel32.net; r...@twiddle.net
Subject: Re: [Qemu
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