(cpu->cfg.ext_svrsw60t59b &&
> +(!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) {
> +error_setg(errp, "svrsw60t59b is not supported on RV32 and MMU-less
> platforms");
> +return;
> +}
> +
> /*
>* Disable isa extensions based on priv spec after we
>* validated and set everything we need.
> @@ -1606,6 +1612,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
>
> if (env->misa_mxl != MXL_RV32) {
> isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
> +} else {
> +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false);
> }
>
> /*
>
> ---
> base-commit: f9a3def17b2a57679902c33064cf7853263db0ef
> change-id: 20250625-dev-alex-svrsw60b59b_v2-a6b7f85be62e
>
> Best regards,
Reviewed-by: Nutty Liu
Thanks,
Nutty
On 6/27/2025 9:20 PM, Max Chou wrote:
> From: Anton Blanchard
>
> Handle the overlap of source registers with different EEWs.
Above description is the same as [patch v2 1/3].
They are different functions.
Maybe need to add some different description.
Otherwise,
Reviewed-by: Nutty Li
. 100 . 1010111 @r_vm_0
> vmsbc_vvm 010011 . . . 000 . 1010111 @r_vm
> vmsbc_vxm 010011 . . ..... 100 . 1010111 @r_vm
> vand_vv 001001 . . . 000 . 1010111 @r_vm
Reviewed-by: Nutty Liu
Thanks,
Nutty
ck)
> @@ -2972,7 +2974,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr
> *a)
> return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_mss(s, a->rd, a->rs1, a->rs2);
> + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
> }
>
> GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
> @@ -2985,7 +2987,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr
> *a)
> return require_rvv(s) &&
> require_rvf(s) &&
> vext_check_isa_ill(s) &&
> - vext_check_ms(s, a->rd, a->rs2);
> + vext_check_ms(s, a->rd, a->rs2, a->vm);
> }
>
> GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
Reviewed-by: Nutty Liu
Thanks,
Nutty
if (cfg->ext_zve32x) {
> +min_vlen = 32;
> +}
> +
> +if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
> error_setg(errp,
> "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
> return;
> }
>
Reviewed-by: Nutty Liu
Thanks,
Nutty
write_mstatush
> },
> -[CSR_MEDELEGH]= { "medelegh", any32, read_zero, write_ignore,
> +[CSR_MEDELEGH]= { "medelegh", smode32, read_zero, write_ignore,
> .min_priv_ver = PRIV_VERSION_1_13_0
> },
> [CSR_HEDELEGH]= { "hedelegh", hmode32, read_hedelegh,
> write_hedelegh,
> .min_priv_ver = PRIV_VERSION_1_13_0
> },
Reviewed-by: Nutty Liu
Thanks,
Nutty
(csrno, 0x300);
>
> -if (!riscv_cpu_cfg(env)->ext_ssaia) {
> +if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
> +return RISCV_EXCP_ILLEGAL_INST;
> +} else if (!riscv_cpu_cfg(env)->ext_ssaia) {
+if ((csr_priv == PRV_M && !riscv_cp
.cfg.ext_ssaia = true,
> +
> +/* RVA23 Profiles */
> +.cfg.ext_zicbom = true,
> +.cfg.ext_zicbop = true,
> +.cfg.ext_zicboz = true,
> +.cfg.ext_svade = true,
> +
> +.cfg.mmu = true,
> +.cfg.pmp = true,
> +
> +.cfg.max_satp_mode = VM_1_10_SV48,
> +),
> +
> #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
> .cfg.max_satp_mode = VM_1_10_SV57,
Reviewed-by: Nutty Liu
Thanks,
Nutty
; + * QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
> + * FPGA prototype platform
> + *
> + * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
> + *
> + */
> +
> +#ifndef HW_XIANGSHAN_KMH_H
> +#define HW_XIANGSHAN_KMH_H
> +
> +#include "hw/boards.h"
> +#include "hw/riscv/riscv_hart.h"
> +
> +#define XIANGSHAN_KMH_MAX_CPUS 16
> +
> +typedef struct XiangshanKmhSoCState {
> +/*< private >*/
> +DeviceState parent_obj;
> +
> +/*< public >*/
> +RISCVHartArrayState cpus;
> +DeviceState *irqchip;
> +MemoryRegion rom;
> +} XiangshanKmhSoCState;
> +
> +#define TYPE_XIANGSHAN_KMH_SOC "xiangshan.kunminghu.soc"
> +DECLARE_INSTANCE_CHECKER(XiangshanKmhSoCState, XIANGSHAN_KMH_SOC,
> + TYPE_XIANGSHAN_KMH_SOC)
> +
> +typedef struct XiangshanKmhState {
> +/*< private >*/
> +MachineState parent_obj;
> +
> +/*< public >*/
> +XiangshanKmhSoCState soc;
> +} XiangshanKmhState;
> +
> +#define TYPE_XIANGSHAN_KMH_MACHINE MACHINE_TYPE_NAME("xiangshan-kunminghu")
> +DECLARE_INSTANCE_CHECKER(XiangshanKmhState, XIANGSHAN_KMH_MACHINE,
> + TYPE_XIANGSHAN_KMH_MACHINE)
> +
> +enum {
> +XIANGSHAN_KMH_ROM,
> +XIANGSHAN_KMH_UART0,
> +XIANGSHAN_KMH_CLINT,
> +XIANGSHAN_KMH_APLIC_M,
> +XIANGSHAN_KMH_APLIC_S,
> +XIANGSHAN_KMH_IMSIC_M,
> +XIANGSHAN_KMH_IMSIC_S,
> +XIANGSHAN_KMH_DRAM,
> +};
> +
> +enum {
> +XIANGSHAN_KMH_UART0_IRQ = 10,
> +};
> +
> +/* Indicating Timebase-freq (1MHZ) */
> +#define XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ 100
> +
> +#define XIANGSHAN_KMH_IMSIC_NUM_IDS 255
> +#define XIANGSHAN_KMH_IMSIC_NUM_GUESTS 7
> +#define XIANGSHAN_KMH_IMSIC_GUEST_BITS 3
> +
> +#define XIANGSHAN_KMH_APLIC_NUM_SOURCES 96
> +
> +#endif
Reviewed-by: Nutty Liu
Thanks,
Nutty
was used to clear S field since this
field is already zero.
Signed-off-by: Nutty Liu
Reviewed-by: Tomasz Jeznach
---
V1 -> V2:
- Commented by Alistair
- Reviewed by Tomasz
- Remove the extra code
---
hw/riscv/riscv-iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --gi
On 6/4/2025 1:52 AM, Tomasz Jeznach wrote:
> On Thu, May 29, 2025 at 2:14 AM Nutty Liu
> wrote:
>> The original implementation incorrectly performed a bitwise AND
>> operation between the PPN of iova and PPN Mask, leading to an
>> incorrect PPN field in Translation-rep
Hi Alistair,
Thanks for your review.
(Sorry, just resend this email due to the incorrect line break in the
previous reply email.)
On 6/2/2025 1:11 PM, Alistair Francis wrote:
> On Thu, May 29, 2025 at 10:52 PM Nutty Liu
> wrote:
>> The original implementation incorrectly perform
The original implementation incorrectly performed a bitwise AND
operation between the PPN of iova and PPN Mask, leading to an
incorrect PPN field in Translation-reponse register.
The PPN of iova should be set entirely in the PPN field of
Translation-reponse register.
Signed-off-by: Nutty Liu
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