> +static struct file *restrictedmem_file_create(struct file *memfd)
> +{
> + struct restrictedmem_data *data;
> + struct address_space *mapping;
> + struct inode *inode;
> + struct file *file;
> +
> + data = kzalloc(sizeof(*data), GFP_KERNEL);
> + if (!data)
> +
On 15/08/22 18:34, Chao Peng wrote:
> On Fri, Aug 12, 2022 at 02:18:43PM +0530, Nikunj A. Dadhania wrote:
>>
>>
>> On 12/08/22 12:48, Gupta, Pankaj wrote:
>>>
>>>>>>>>
>>>>>>>> However, fallocate() preallocates full
On 12/08/22 12:48, Gupta, Pankaj wrote:
>
>>
>> However, fallocate() preallocates full guest memory before starting the
>> guest.
>> With this behaviour guest memory is *not* demand pinned. Is there a way
>> to
>> prevent fallocate() from reserving full guest memory?
>
On 11/08/22 19:02, Chao Peng wrote:
> On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote:
>>>
>>> While debugging an issue with SEV+UPM, found that fallocate() returns
>>> an error in QEMU which is not handled (EINTR). With the below handling
>>> of EINTR subsequent fallocate() succee
On 11/08/22 19:02, Chao Peng wrote:
> On Thu, Aug 11, 2022 at 01:30:06PM +0200, Gupta, Pankaj wrote:
>>
Test
To test the new functionalities of this patch TDX patchset is needed.
Since TDX patchset has not been merged so I did two kinds of test:
- Regresion test
On 11/08/22 17:00, Gupta, Pankaj wrote:
>
>>> This is the v7 of this series which tries to implement the fd-based KVM
>>> guest private memory. The patches are based on latest kvm/queue branch
>>> commit:
>>>
>>> b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU
>>> split_desc_cache only
On 06/07/22 13:50, Chao Peng wrote:
> This is the v7 of this series which tries to implement the fd-based KVM
> guest private memory. The patches are based on latest kvm/queue branch
> commit:
>
> b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU
> split_desc_cache only by default capacit
On 7/18/2022 7:15 PM, Joao Martins wrote:
> On 7/18/22 14:10, Nikunj A. Dadhania wrote:
>> On 7/18/2022 6:12 PM, Igor Mammedov wrote:
>>> On Mon, 18 Jul 2022 13:47:34 +0530
>>> Nikunj A Dadhania wrote:
>>>
>>>> Currently it is possible to s
On 7/18/2022 6:12 PM, Igor Mammedov wrote:
> On Mon, 18 Jul 2022 13:47:34 +0530
> Nikunj A Dadhania wrote:
>
>> Currently it is possible to start a guest with memory that is beyond
>> the addressable range of CPU and QEMU does not even warn about it.
>> The defa
.
Reported-by: Shaju Abraham
Signed-off-by: Nikunj A Dadhania
---
target/i386/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a57ef13af..1afbdbac7d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6376,6 +6376,7
On 5/19/2022 9:07 PM, Chao Peng wrote:
> A page fault can carry the information of whether the access if private
> or not for KVM_MEM_PRIVATE memslot, this can be filled by architecture
> code(like TDX code). To handle page faut for such access, KVM maps the
> page only when this private property m
David Gibson writes:
> On Tue, Sep 04, 2018 at 11:00:39AM +0530, Nikunj A Dadhania wrote:
>> Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is
>> online(1) or offline(0)
>>
>> KVM will use this information to set the RWMR register, which c
Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is
online(1) or offline(0)
KVM will use this information to set the RWMR register, which controls the PURR
and SPURR accumulation.
CC: pau...@samba.org
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr_cpu_core.c | 1
Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is
online(1) or offline(0)
KVM will use this information to set the RWMR register, which controls the PURR
and SPURR accumulation.
CC: pau...@samba.org
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr_cpu_core.c | 1
David Gibson writes:
> On Mon, Apr 23, 2018 at 11:43:02AM +0530, Nikunj A Dadhania wrote:
>> Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is
>> online(1) or offline(0)
>>
>> KVM will use this information to set the RWMR register, which c
Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is
online(1) or offline(0)
KVM will use this information to set the RWMR register, which controls the PURR
and SPURR accumulation.
CC: pau...@samba.org
Signed-off-by: Nikunj A Dadhania
---
http://patchwork.ozlabs.org
Richard Henderson writes:
> On 03/16/2018 12:08 PM, Nikunj A Dadhania wrote:
>> @@ -1078,8 +1079,8 @@ struct CPUPPCState {
>> /* Altivec registers */
>> ppc_avr_t avr[32];
>> uint32_t vscr;
>> -/* VSX registers */
>> -uint64_t vsr[32]
Richard Henderson writes:
> On 03/07/2018 06:03 PM, Nikunj A Dadhania wrote:
>> Hi Richard,
>>
>> I was working to get TCG vector support for PowerPC[1]. Started with
>> converting logical operations like vector AND/OR/XOR and compare
>> instructions. Found som
Hi Richard,
I was working to get TCG vector support for PowerPC[1]. Started with
converting logical operations like vector AND/OR/XOR and compare
instructions. Found some inconsistency during my testing on x86 laptop
emulating PowerPC:
zero =
max = f
compatible with existing/older firmware. This older property
can be deprecated after 5 years.
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/e500.c | 7 +++
hw/ppc/spapr.c | 7 +++
2 files changed, 14 insertions(+)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index a40d3ec3e3..a325a95015 10064
or
> the secondaries.
>
> Based on previous work from Nikunj A Dadhania
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Nikunj A Dadhania
> ---
> hw/ppc/spapr_cpu_core.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/ppc/spapr_cpu_cor
Benjamin Herrenschmidt writes:
> On Fri, 2017-10-06 at 11:40 +0530, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>> > Hello,
>> >
>> > When a CPU is stopped with the 'stop-self' RTAS call, its state
>> > 'hal
Cédric Le Goater writes:
> Hello,
>
> When a CPU is stopped with the 'stop-self' RTAS call, its state
> 'halted' is switched to 1 and, in this case, the MSR is not taken into
> account anymore in the cpu_has_work() routine. Only the pending
> hardware interrupts are checked with their LPCR:PECE*
Cédric Le Goater writes:
> On 09/22/2017 08:00 AM, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>>>>>>
>>>>>> As smp_thread defaults to 1 in vl.c, similarly smp_cores also has the
>>>>>> default valu
When the user does not provide the cpu topology, e.g. "-smp 4", machine
fails to
initialize 4 cpus. QEMU assumes smp_threads and smp_cores both as 1. Make
sure
that we initialize multiple chips for this.
Remove the user-settable property num_chips from machi
David Gibson writes:
> On Wed, Sep 20, 2017 at 12:48:55PM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Wed, Sep 20, 2017 at 12:10:48PM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >> &
David Gibson writes:
> On Wed, Sep 20, 2017 at 12:10:48PM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Wed, Sep 20, 2017 at 10:43:19AM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >> &
Nikunj A Dadhania writes:
>> >>
>>> >> I think the current approach is the simplest and less intrusive, as we
>>> >> are handling a case where user has not bothered to provide a detailed
>>> >> topology, the best we can do is cre
David Gibson writes:
> On Wed, Sep 20, 2017 at 10:43:19AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Wed, Sep 20, 2017 at 09:50:24AM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >> &
David Gibson writes:
> On Wed, Sep 20, 2017 at 09:50:24AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Fri, Sep 15, 2017 at 02:39:16PM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >> &
David Gibson writes:
> On Fri, Sep 15, 2017 at 02:39:16PM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Fri, Sep 15, 2017 at 01:53:15PM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >>
David Gibson writes:
> On Fri, Sep 15, 2017 at 01:53:15PM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> >>
>> >> I thought, I am doing the same here for PowerNV, number of online cores
>> >> is equal to initial online vcpus /
David Gibson writes:
>>
>> I thought, I am doing the same here for PowerNV, number of online cores
>> is equal to initial online vcpus / threads per core
>>
>>int boot_cores_nr = smp_cpus / smp_threads;
>>
>> Only difference that I see in PowerNV is that we have multiple chips
>> (max 2, a
David Gibson writes:
> On Wed, Jul 19, 2017 at 09:20:52AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote:
>> >> David Gibson writes:
>> >>
>> >> &
David Gibson writes:
> On Mon, Sep 11, 2017 at 10:40:10AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Wed, Sep 06, 2017 at 01:57:48PM +0530, Nikunj A Dadhania wrote:
>> >> When the user does not provide the cpu topology, e.
David Gibson writes:
> On Wed, Sep 06, 2017 at 01:57:48PM +0530, Nikunj A Dadhania wrote:
>> When the user does not provide the cpu topology, e.g. "-smp 4", machine
>> fails to
>> initialize 4 cpus. Compute the chip per cores depending on the number
When the user does not provide the cpu topology, e.g. "-smp 4", machine fails to
initialize 4 cpus. Compute the chip per cores depending on the number of chips
and smt threads.
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/pnv.c | 20 ++--
1 file changed, 18 insert
David Gibson writes:
> On Wed, Aug 16, 2017 at 02:42:13PM +0530, Aravinda Prasad wrote:
>> Receive updates from SLOF about the updated rtas-base.
>> A separate patch for SLOF [1] adds functionality to invoke
>> a private HCALL whenever OS issues instantiate-rtas with
>> a new rtas-base.
>>
>> Th
David Gibson writes:
> On Tue, Jul 18, 2017 at 10:53:01AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote:
>> >> Rebooting a SMP TCG guest is broken for both single/multi t
David Gibson writes:
> On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote:
>> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG.
>>
>> When reset happens, all the CPUs are in halted state. First CPU is brought
>> out
>> of
David Gibson writes:
> On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote:
>> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG.
>>
>> When reset happens, all the CPUs are in halted state. First CPU is brought
>> out
>> of
David Gibson writes:
> On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote:
>> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG.
>>
>> When reset happens, all the CPUs are in halted state. First CPU is brought
>> out
>> of
rtas start-cpu call.
Reported-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
---
hw/ppc/spapr_cpu_core.c | 9 +
hw/ppc/spapr_rtas.c | 8
2 files changed, 17 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index ea278ce..bbfe8c2 100644
--- a
= 4bd8
ERROR: Flatten device tree not available!
exception 300
SRR0 = 60e4 SRR1 = 80008000
SPRG2 = 0040 SPRG3 = 4bd8
Reported-by: Bharata B Rao
Tested-by: Cédric Le Goater
Signed-off-by: Nikunj A Dadhania
---
target/ppc/translate_init.c
Cédric Le Goater writes:
> On 07/13/2017 11:10 AM, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>> On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote:
>>>> Cédric Le Goater writes:
>>>>
>>>>>>> Ho
Nikunj A Dadhania writes:
> Cédric Le Goater writes:
>
>> On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote:
>>> Cédric Le Goater writes:
>>>
>>>>>> How about the following, we do not report work until MSR_EE is disabled:
>>>>>
&
Cédric Le Goater writes:
> On 07/13/2017 09:55 AM, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>>>> How about the following, we do not report work until MSR_EE is disabled:
>>>>
>>>> With this fix, I could test the XIVE<-
Cédric Le Goater writes:
>>> How about the following, we do not report work until MSR_EE is disabled:
>>
>> With this fix, I could test the XIVE<->XICS transitions at reboot
>> under TCG. However, the second boot is very slow for some reason.
>
> hmm, I am not sure this is related but I just g
Cédric Le Goater writes:
> On 07/13/2017 06:38 AM, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>>>
>>> Ok, but we definitely should be able to fix this without new
>>> variables. If we can quiesce the secondary CPUs for the first boot,
&
David Gibson writes:
> On Fri, Jun 09, 2017 at 10:32:25AM +0530, Nikunj A Dadhania wrote:
>> David Gibson writes:
>>
>> > On Thu, Jun 08, 2017 at 12:06:08PM +0530, Nikunj A Dadhania wrote:
>> >> Rebooting a SMP TCG guest is broken for both single/multi
Nikunj A Dadhania writes:
> Greg Kurz writes:
>
>> On Sun, 11 Jun 2017 17:38:42 +0800
>> David Gibson wrote:
>>
>>> On Fri, Jun 09, 2017 at 05:09:13PM +0200, Greg Kurz wrote:
>>> > On Fri, 9 Jun 2017 20:28:32 +1000
>>> > David Gibson w
Alex Bennée writes:
> Thomas Huth writes:
>
>> Since the introduction of MTTCG, using the msgsnd instruction
>> abort()s if being called without holding the BQL. So let's protect
>> that part of the code now with qemu_mutex_lock_iothread().
>>
>> Buglink: https://bugs.launchpad.net/qemu/+bug/169
David Gibson writes:
> On Tue, Jun 13, 2017 at 01:59:29PM +0530, Nikunj A Dadhania wrote:
>> Greg Kurz writes:
>>
>> > On Sun, 11 Jun 2017 17:38:42 +0800
>> > David Gibson wrote:
>> >
>> >> On Fri, Jun 09, 2017 at 05:09:13PM +0200, Greg
t;> > -drive file=/home/greg/images/sle12-sp1-ppc64le.qcow2,id=drive0,if=none \
>> > -machine type=pseries,accel=tcg -cpu POWER8
Strangely, your command line does not have multiple threads. Need to see
what is the side effect of enabling MTTCG by default here.
>> >
>>
David Gibson writes:
> On Thu, Jun 08, 2017 at 12:06:08PM +0530, Nikunj A Dadhania wrote:
>> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG.
>
> Ouch. When exactly did this happen?
Broken since long
> I know that smp boot used to work under TCG,
= 4bd8
ERROR: Flatten device tree not available!
exception 300
SRR0 = 60e4 SRR1 = 80008000
SPRG2 = 0040 SPRG3 = 4bd8
Reported-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
---
Note: Similar changes would be required for powernv as
Peter Maydell writes:
> Commit c10b97092 changed some field names in rldicr and rldimi patterns
> but forgot to update the constraints to match the change. Since the
> field (previously 'rb' and now 'sh') is an immediate rather than a
> register number, the correct fix is to just delete the const
Peter Maydell writes:
> On 30 May 2017 at 16:39, Peter Maydell wrote:
>> On 30 May 2017 at 16:26, Nikunj A Dadhania wrote:
>>> Sandipan Das writes:
>>>
>>>> The patterns for the following instructions are fixed:
>>>> * Rotate Left Doublew
first instruction has a typo. For the other two instructions,
> the extended opcodes are incorrect and the shift field 'sha' is
> absent. Also, the shift field 'sh' should be used in place of the
> register field 'rb'.
>
> Signed-off-by: Sandipan
G 3 writes:
> On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:
>
> Hello I have also done some work risu. My patches add ppc32 support.
> Well my patches were made to work with Mac OS X but they are required
> to work with Linux. Do you think you could help port these patches
Sandipan Das writes:
> The patterns for the following instructions are fixed:
> * Rotate Left Doubleword then Clear Right (rldcr[.])
> * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
> * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>
> Signed-off-by: Sandipan D
For transitioning back to userspace after the interrupt.
Suggested-by: Richard Henderson
Signed-off-by: Nikunj A Dadhania
---
target/ppc/excp_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a6bcb47..9cb2123 100644
--- a
Philippe Mathieu-Daudé writes:
> Applied using Coccinelle script.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/ppc/translate.c | 9 +++--
> target/ppc/translate/vsx-impl.inc.c | 21 +++--
> 2 files changed, 10 insertions(+), 20 deletions(-)
>
> diff
t by the time it return back, the reservation is erased and the code
fails, this continues forever and the lock is never taken.
Instead set this in powerpc_excp()
Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do,
let us get rid of the function.
Signed-off-by: Nikunj A D
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
---
target/ppc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4d..4a1f24a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
From: Bharata B Rao
Ensure that the unplugged CPU thread is destroyed and the waiting
thread is notified about it. This is needed for CPU unplug to work
correctly in MTTCG mode.
Signed-off-by: Bharata B Rao
Signed-off-by: Nikunj A Dadhania
---
cpus.c | 6 ++
1 file changed, 6 insertions
Emulating LL/SC with cmpxchg is not correct, since it can suffer from
the ABA problem. However, portable parallel code is written assuming
only cmpxchg which means that in practice this is a viable alternative.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard Henderson
---
target/ppc
In case where the conditional write is the first write to the page,
TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as
a special case and set the dirty bit. After that fall through to the
actual atomic instruction below.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard
This enables the multi-threaded system emulation by default for PPC64
guests using the x86_64 TCG back-end.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Alex Bennée
---
configure| 2 ++
target/ppc/cpu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configure b/configure
index
turn value after exit_atomic
* Fixed a bug in ppc_cpu_exec_enter(), which was resetting the
reserve_addr, this should be done in powerpc_excp()
v1:
* Rewrote store_conditional as suggested by Richard
Bharata B Rao (1):
cpus: Fix CPU unplug for MTTCG
Nikunj A Dadhania (5):
target/ppc: Emu
t by the time it return back, the reservation is erased and the code
fails, this continues forever and the lock is never taken.
Instead set this in powerpc_excp()
Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do,
let us get rid of the function.
Signed-off-by: Nikunj A Dadh
Richard Henderson writes:
> Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize
> the output. Even though this code is dead, it gets translated, and
> without the initialization we encounter a tcg_error.
>
> Reported-by: Nikunj A Dadhania
> Signed-off-by:
Nikunj A Dadhania writes:
> aNikunj A Dadhania writes:
>
>> Richard Henderson writes:
>>
>>> On 04/25/2017 01:21 PM, Nikunj A Dadhania wrote:
>>>> Richard Henderson writes:
>>>>
>>>>> Users of tcg_gen_atomic_cmpxchg and do_ato
aNikunj A Dadhania writes:
> Richard Henderson writes:
>
>> On 04/25/2017 01:21 PM, Nikunj A Dadhania wrote:
>>> Richard Henderson writes:
>>>
>>>> Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize
>>>> the output.
Richard Henderson writes:
> Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize
> the output. Even though this code is dead, it gets translated, and
> without the initialization we encounter a tcg_error.
>
> Reported-by: Nikunj A Dadhania
> Signed-off-by:
Peter Maydell writes:
> On 25 April 2017 at 09:58, Nikunj A Dadhania
> wrote:
>> I was trying out the program in the configure script with clang and I do
>> get errors without libatomic:
>>
>> $ clang /tmp/atomic.c
>> /tmp/atomic.c:6:7: warni
Peter Maydell writes:
> On 25 April 2017 at 09:35, Nikunj A Dadhania
> wrote:
>> Travis builds failure was reported for powernv boot-serial test with
>> qemu built with clang.
>>
>> Debugging revealed that CONFIG_ATOMIC64 wasnt getting set for the clang
&
test.
libatomic is required to successfully test atomic64 and atomic128 for
clang. Introduced newer checks for the same. And on failure default to
single threaded tcg support in PPC64.
Signed-off-by: Nikunj A Dadhania
---
Reference:
https://lists.gnu.org/archive/html/qemu-ppc/2017-04/msg00277
Cédric Le Goater writes:
> On 04/10/2017 06:44 PM, Nikunj A Dadhania wrote:
>> Cédric Le Goater writes:
>>
>>> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
>>>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
>>>>> Cédric Le Goater wri
Cédric Le Goater writes:
> On 04/07/2017 08:07 AM, Cédric Le Goater wrote:
>> On 04/07/2017 07:24 AM, Nikunj A Dadhania wrote:
>>> Cédric Le Goater writes:
>>>
>>>> Hello Nikunj,
>>>>
>>>> On 04/06/2017 12:22 PM, Nikunj A Dadha
This enables the multi-threaded system emulation by default for PPC64
guests using the x86_64 TCG back-end.
Signed-off-by: Nikunj A Dadhania
---
Depends on following patch which fixes the define name:
https://patchwork.ozlabs.org/patch/748840/
---
configure| 2 ++
target/ppc/cpu.h
Alex Bennée writes:
> Nikunj A Dadhania writes:
>
>> Alex Bennée writes:
>>
>>> luigi burdo writes:
>>>
>>>> Hi David and Nikuji,
>>>>
>>>> can i suggest to remove the message:
>>>>
>>>>
>&g
While the configure script generates TARGET_SUPPORTS_MTTCG define, one
of the define is cpus.c is checking wrong name: TARGET_SUPPORT_MTTCG
Signed-off-by: Nikunj A Dadhania
---
cpus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cpus.c b/cpus.c
index 68fdbc4..58d90aa
Alex Bennée writes:
> luigi burdo writes:
>
>> Hi David and Nikuji,
>>
>> can i suggest to remove the message:
>>
>>
>> Guest not yet converted to MTTCG - you may get unexpected results
>> where the mttcg is enabled?
>
> Have you declared the memory ordering for the guest?
No, I havent done tha
Signed-off-by: Nikunj A Dadhania
---
target/ppc/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4d..4a1f24a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2971,6 +2971,7 @@ static void
Emulating LL/SC with cmpxchg is not correct, since it can suffer from
the ABA problem. However, portable parallel code is written assuming
only cmpxchg which means that in practice this is a viable alternative.
Signed-off-by: Nikunj A Dadhania
---
target/ppc/translate.c | 29
.
* More testing for corner cases.
Nikunj A Dadhania (3):
target/ppc: Emulate LL/SC using cmpxchg helpers
cputlb: handle first atomic write to the page
target/ppc: Generate fence operations
cputlb.c | 8 +++-
target/ppc/translate.c | 37
In case where the conditional write is the first write to the page,
TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as
a special case and set the dirty bit. After that fall through to the
actual atomic instruction below.
Signed-off-by: Nikunj A Dadhania
Reviewed-by: Richard
David Gibson writes:
> [ Unknown signature status ]
> On Thu, Apr 06, 2017 at 03:52:47PM +0530, Nikunj A Dadhania wrote:
>> Emulating LL/SC with cmpxchg is not correct, since it can suffer from
>> the ABA problem. However, portable parallel code is written assuming
>>
Cédric Le Goater writes:
> Hello Nikunj,
>
> On 04/06/2017 12:22 PM, Nikunj A Dadhania wrote:
>> The series enables Multi-Threaded TCG on PPC64
>>
>> Patch 01: Use atomic_cmpxchg in store conditional
>> 02: Handle first write to page during atomic opera
Richard Henderson writes:
> On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote:
>> @@ -3028,6 +3030,7 @@ static void gen_##name(DisasContext *ctx)
>> \
>> tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop);\
>>
Richard Henderson writes:
> On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote:
>> tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
>> l1 = gen_new_label();
>> tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
>> -tcg_gen_ori_i32(cpu
Richard Henderson writes:
> On 04/06/2017 03:22 AM, Nikunj A Dadhania wrote:
>> +TCGv_i32 tmp = tcg_temp_local_new_i32();
>> +TCGv t0;
>>
>> +tcg_gen_movi_i32(tmp, 0);
>> tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
>> l1 = gen
Emulating LL/SC with cmpxchg is not correct, since it can suffer from
the ABA problem. However, portable parallel code is written assuming
only cmpxchg which means that in practice this is a viable alternative.
Signed-off-by: Nikunj A Dadhania
---
target/ppc/translate.c | 24
In case where the conditional write is the first write to the page,
TLB_NOTDIRTY will be set and stop_the_world is triggered. Handle this as
a special case and set the dirty bit. After that fall through to the
actual atomic instruction below.
Signed-off-by: Nikunj A Dadhania
---
cputlb.c | 8
:
./ppc64-softmmu/qemu-system-ppc64 -cpu POWER8 -vga none -nographic -machine
pseries,usb=off -m 2G -smp 8,cores=8,threads=1 -accel tcg,thread=multi f23.img
Todo:
* Enable other machine types and PPC32.
* More testing for corner cases.
Nikunj A Dadhania (3):
target/ppc: Emulate LL/SC using
Signed-off-by: Nikunj A Dadhania
---
target/ppc/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a9c733d..87b4fe4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2971,6 +2971,7 @@ static void gen_stswx
Alex Bennée writes:
> Nikunj A Dadhania writes:
>
>> Richard Henderson writes:
>>
>>> On 09/12/2016 06:47 AM, Alex Bennée wrote:
>>>>> > +/* Notice an IO access, or a notdirty page. */
>>>>> > +if (unlikely(tlb_addr &am
Alex Bennée writes:
> Nikunj A Dadhania writes:
>
>> Richard Henderson writes:
>>
>>> On 09/12/2016 06:47 AM, Alex Bennée wrote:
>>>>> > +/* Notice an IO access, or a notdirty page. */
>>>>> > +if (unlikely(tlb_addr &am
Richard Henderson writes:
> On 09/12/2016 06:47 AM, Alex Bennée wrote:
>>> > +/* Notice an IO access, or a notdirty page. */
>>> > +if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
>>> > +/* There's really nothing that can be done to
>>> > + support this apart from stop-th
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