Re: [PATCH v8 04/10] hw/intc: GICv3 ITS Command processing

devid = 0; > + > +switch (offset) { > +case GITS_TRANSLATER: > +if (s->ctlr & ITS_CTLR_ENABLED) { > +devid = attrs.requester_id; > +result = process_its_cmd(s, data, devid, NONE); > +} > +break; > +defau

[PATCH] misc: edu: add MSI-X interrupt generation aswell

Add MSI-X aswell since either MSI or MSI-X are optional and MSI can still be used without any issues. Signed-off-by: Neil Armstrong --- hw/misc/edu.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/misc/edu.c b/hw/misc/edu.c index e935c418d4..5d0643e1bd

Re: [PATCH v7 05/10] hw/intc: GICv3 ITS Feature enablement

(1U << 31) > > +#define GICD_TYPER_LPIS_SHIFT 17 > + > /* 16 bits EventId */ > #define GICD_TYPER_IDBITS0xf > > diff --git a/include/hw/intc/arm_gicv3_common.h > b/include/hw/intc/arm_gicv3_common.h > index 0715b0bc2a..c1348cc60a 100644 > --- a/include/hw/intc/arm_gicv3_common.h > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -221,6 +221,7 @@ struct GICv3State { > uint32_t num_cpu; > uint32_t num_irq; > uint32_t revision; > +bool lpi_enable; > bool security_extn; > bool irq_reset_nonsecure; > bool gicd_no_migration_shift_bug; > Tested with in-review Zephyr ITS implementation at https://github.com/zephyrproject-rtos/zephyr/pull/37506 Tested-by: Neil Armstrong

Re: [PATCH v7 02/10] hw/intc: GICv3 ITS register definitions added

GITS_BASER_PAGESIZE_4K0 > #define GITS_BASER_PAGESIZE_16K 1 > #define GITS_BASER_PAGESIZE_64K 2 > @@ -276,6 +297,14 @@ FIELD(GITS_TYPER, CIL, 36, 1) > #define GITS_BASER_TYPE_DEVICE 1ULL > #define GITS_BASER_TYPE_COLLECTION 4ULL > > +#define GITS_PAGE_SIZE_4K 0x1000 > +#define GITS_PAGE_SIZE_16K 0x4000 > +#define GITS_PAGE_SIZE_64K 0x1 > + > +#define L1TABLE_ENTRY_SIZE 8 > + > +#define GITS_CMDQ_ENTRY_SIZE 32 > + > /** > * Default features advertised by this version of ITS > */ > diff --git a/include/hw/intc/arm_gicv3_common.h > b/include/hw/intc/arm_gicv3_common.h > index 91491a2f66..1fd5cedbbd 100644 > --- a/include/hw/intc/arm_gicv3_common.h > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -226,6 +226,9 @@ struct GICv3State { > int dev_fd; /* kvm device fd if backed by kvm vgic support */ > Error *migration_blocker; > > +MemoryRegion *dma; > +AddressSpace dma_as; > + > /* Distributor */ > > /* for a GIC with the security extensions the NS banked version of this > diff --git a/include/hw/intc/arm_gicv3_its_common.h > b/include/hw/intc/arm_gicv3_its_common.h > index 65d1191db1..4e79145dde 100644 > --- a/include/hw/intc/arm_gicv3_its_common.h > +++ b/include/hw/intc/arm_gicv3_its_common.h > @@ -41,6 +41,25 @@ > > #define GITS_TRANSLATER 0x0040 > > +typedef struct { > +bool valid; > +bool indirect; > +uint16_t entry_sz; > +uint32_t page_sz; > +uint32_t max_entries; > +union { > +uint32_t max_devids; > +uint32_t max_collids; > +} maxids; > +uint64_t base_addr; > +} TableDesc; > + > +typedef struct { > +bool valid; > +uint32_t max_entries; > +uint64_t base_addr; > +} CmdQDesc; > + > struct GICv3ITSState { > SysBusDevice parent_obj; > > @@ -63,6 +82,10 @@ struct GICv3ITSState { > uint64_t creadr; > uint64_t baser[8]; > > +TableDesc dt; > +TableDesc ct; > +CmdQDesc cq; > + > Error *migration_blocker; > }; > > Tested with in-review Zephyr ITS implementation at https://github.com/zephyrproject-rtos/zephyr/pull/37506 Tested-by: Neil Armstrong

Re: [PATCH v7 03/10] hw/intc: GICv3 ITS command queue framework

CMD_CLEAR0x04 > +#define GITS_CMD_DISCARD 0x0F > +#define GITS_CMD_INT 0x03 > +#define GITS_CMD_MAPC 0x09 > +#define GITS_CMD_MAPD 0x08 > +#define GITS_CMD_MAPI 0x0B > +#define GITS_CMD_MAPTI0x0A > +#defin

Re: [PATCH v7 06/10] hw/intc: GICv3 redistributor ITS processing

32 > #define NUM_BYTES_IN_DW 8 > > @@ -397,6 +402,7 @@ FIELD(MAPC, RDBASE, 16, 32) > * Valid = 1 bit,RDBase = 36 bits(considering max RDBASE) > */ > #define GITS_CTE_SIZE (0x8ULL) > +#define GITS_CTE_RDBASE_PROCNUM_MASK MAKE_64BIT_MASK(1, > RDBASE_PROCNUM_LENGTH) > > /* Special interrupt IDs */ > #define INTID_SECURE 1020 > @@ -455,6 +461,9 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr > offset, uint64_t data, > unsigned size, MemTxAttrs attrs); > void gicv3_dist_set_irq(GICv3State *s, int irq, int level); > void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); > +void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); > +void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); > +void gicv3_redist_update_lpi(GICv3CPUState *cs); > void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); > void gicv3_init_cpuif(GICv3State *s); > > diff --git a/include/hw/intc/arm_gicv3_common.h > b/include/hw/intc/arm_gicv3_common.h > index c1348cc60a..aa4f0d6770 100644 > --- a/include/hw/intc/arm_gicv3_common.h > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -204,6 +204,13 @@ struct GICv3CPUState { > * real state above; it doesn't need to be migrated. > */ > PendingIrq hppi; > + > +/* > + * Cached information recalculated from LPI tables > + * in guest memory > + */ > +PendingIrq hpplpi; > + > /* This is temporary working state, to avoid a malloc in gicv3_update() > */ > bool seenbetter; > }; > Tested with in-review Zephyr ITS implementation at https://github.com/zephyrproject-rtos/zephyr/pull/37506 Tested-by: Neil Armstrong

Re: [PATCH v7 01/10] hw/intc: GICv3 ITS initial framework

; --- a/hw/intc/meson.build > +++ b/hw/intc/meson.build > @@ -8,6 +8,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( >'arm_gicv3_dist.c', >'arm_gicv3_its_common.c', >'arm_gicv3_redist.c', > + 'arm_gicv3_its.c', > )) > softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) > softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) > diff --git a/include/hw/intc/arm_gicv3_its_common.h > b/include/hw/intc/arm_gicv3_its_common.h > index 5a0952b404..65d1191db1 100644 > --- a/include/hw/intc/arm_gicv3_its_common.h > +++ b/include/hw/intc/arm_gicv3_its_common.h > @@ -25,17 +25,22 @@ > #include "hw/intc/arm_gicv3_common.h" > #include "qom/object.h" > > +#define TYPE_ARM_GICV3_ITS "arm-gicv3-its" > + > #define ITS_CONTROL_SIZE 0x1 > #define ITS_TRANS_SIZE 0x1 > #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) > > #define GITS_CTLR0x0 > #define GITS_IIDR0x4 > +#define GITS_TYPER 0x8 > #define GITS_CBASER 0x80 > #define GITS_CWRITER 0x88 > #define GITS_CREADR 0x90 > #define GITS_BASER 0x100 > > +#define GITS_TRANSLATER 0x0040 > + > struct GICv3ITSState { > SysBusDevice parent_obj; > > @@ -52,6 +57,7 @@ struct GICv3ITSState { > /* Registers */ > uint32_t ctlr; > uint32_t iidr; > +uint64_t typer; > uint64_t cbaser; > uint64_t cwriter; > uint64_t creadr; > @@ -62,7 +68,8 @@ struct GICv3ITSState { > > typedef struct GICv3ITSState GICv3ITSState; > > -void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops); > +void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, > + const MemoryRegionOps *tops); > > #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common" > typedef struct GICv3ITSCommonClass GICv3ITSCommonClass; > Tested with in-review Zephyr ITS implementation at https://github.com/zephyrproject-rtos/zephyr/pull/37506 Tested-by: Neil Armstrong

Re: [PATCH v7 04/10] hw/intc: GICv3 ITS Command processing

Hi, On 06/08/2021 00:29, Shashi Mallela wrote: > Added ITS command queue handling for MAPTI,MAPI commands,handled ITS > translation which triggers an LPI via INT command as well as write > to GITS_TRANSLATER register,defined enum to differentiate between ITS > command interrupt trigger and GITS_TR