Question about TLBs

2022-12-31 Thread Nada Lachtar
Hello, Does Qemu maintain two TLB for the x86_64 system (i.e iTLB and dTLB)? If yes, can you please point me to how to access the dTLB and what data structure maintains this information! I would appreciate any help, Thanks, smime.p7s Description: S/MIME cryptographic signature

Question about CPUTLBEntry

2022-11-30 Thread Nada Lachtar
Hello, I’m trying to understand the structure of TLB in QEMU/tcg, in order to extract the physical address from the CPUTLBEntry. Would this be possible without having the virtual address and use tlb_lookup? For example, I would like to read all the physical addresses that are recorded in the

Read/write into the guest RAM

2022-08-06 Thread Nada Lachtar
Hello, Can I get some clarity about the fast path load/store to RAM memory for x86 systems guest? I would like to understand more about how Qemu read/write into the guest RAM? I’m trying to implement a type of cache to record the addresses being accessed by load/store instructions. Thank you

Question about RAM and block data

2022-06-23 Thread Nada Lachtar
Hello, I’m trying to trace the physical address in the RAM for some data that is being written to a block device. I have access to the QEMUIOVector buffer that hold that data. However, I’m not sure how to trace how’s it being written from the RAM to the buffer, and how to get the physical addre

Storage controller access to data

2021-10-12 Thread Nada Lachtar
Hello, I’m working on a project that requires me to read the data being sent to storage and it to a file for analysis. To be more specific, I’m trying to analyze the data in the phase of being written to the storage disk, thus, I’m trying to read the data when it’s going through a storage contr