Re: [v5, 5/6] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO

> There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1 > register in the SCUIO (IO DIE). The values of these two registers should not > be > the same. To reuse the current design of hw-strap, hw-strap1 is assigned to > the > SCU and sets the value in the SCU hw-strap1 regist

Re: [v5, 3/6] hw/arm/aspeed Update HW Strap Default Values for AST2700

> Separate HW Strap Registers for SCU and SCUIO. > AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1. > AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1. > > Additionally, both default values are updated based on the dump from the EVB. > > Signed-off-by: Jamin Lin > Rev

Re: [v5, 2/6] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700

> According to the design of the AST2600, it has a Silicon Revision ID Register, > specifically SCU004 and SCU014, to set the Revision ID for the AST2600. > For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to > 0x05030303. > In the "aspeed_ast2600_scu_reset" function, the hardcode