explicitly installed.
Thanks,
Nabih
Nabih Estefan (he/him) | Software Engineer |
nabiheste...@google.com | 857-308-9574
On Mon, Jun 2, 2025 at 11:41 AM Pierrick Bouvier
wrote:
>
> Hi Cédric,
>
> On 6/2/25 6:59 AM, Cédric Le Goater wrote:
> > Hello Pierrick,
> >
> &g
This patch series modifies the gdbstub to address a bug running a
multi cluster machine in QEMU using TCG. The machine where the
problem was seen had several clusters of CPUs with similar
architectures and similar memory layout all working with physical
addresses. It was discovered under gdb debugg
he patch needs to expose the currently private function
gdb_get_cpu_pid to the TCG and also expose the value of
gdbserver_state.multiprocess. The PID filtering will only be
applicable to multiprocess gdb because the PIDs are only defined in
that context.
Signed-off-by: Roque Arcudia Hernandez
Signed-o
und a comment that says:
/* Make sure the remote is pointing at the right process, if
necessary. */
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
gdbstub/gdbstub.c | 4 ++--
gdbstub/internals.h | 13 +++--
2 files changed, 13 insertions(+), 4
From: Peter Foley
e.g.
Uninitialized value was created by an allocation of 'host_pc' in the stack
frame
#0 0xc07df87c in tb_gen_code
third_party/qemu/accel/tcg/translate-all.c:297:5
Signed-off-by: Peter Foley
Signed-off-by: Nabih Estefan
---
accel/tcg/translate-all.c | 2
Fixes for miscellaneous msan finding in QEMU
Peter Foley (2):
util: fix msan findings in keyval
accel/tcg: fix msan findings in translate-all
accel/tcg/translate-all.c | 2 +-
util/keyval.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
2.49.0.1015.ga840276032-goog
49f489c in keyval_parse_one third_party/qemu/util/keyval.c:190:5
Signed-off-by: Peter Foley
Signed-off-by: Nabih Estefan
---
util/keyval.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/keyval.c b/util/keyval.c
index a70629a481..f33c64079d 100644
--- a/util/keyval.c
+++ b/uti
For upstreaming we migrated this test to 7xx (since that was already
upstream) move it back to 8xx where it can check the 4 GMACs since that
is the board this test was originally created for.
Signed-off-by: Nabih Estefan
---
tests/qtest/meson.build | 6 ++-
tests/qtest/npcm_gmac-test.c
This is a set of patches to add the GMAC devices to the 8xx board and
migrate the GMAC tests to 8xx, which is how they were originally
created.
Hao Wu (1):
hw/arm: Add GMAC devices to NPCM8XX SoC
Nabih Estefan Diaz (1):
tests/qtest: Migrate GMAC test from 7xx to 8xx
hw/arm/npcm8xx.c
From: Hao Wu
The GMAC was originally created for the 8xx machine. During upstreaming
both the GMAC and the 8XX we removed it so they would not depend on each
other for the process, that connection should be added back in.
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
---
hw/arm
On Wed, Apr 30, 2025 at 5:03 AM Peter Maydell wrote:
>
> On Tue, 29 Apr 2025 at 16:56, Nabih Estefan wrote:
> >
> > v2: used ldl_le_p and lduw_l_p instead of memcpy as per upstream
> > suggestion.
> >
> > ```
> > ../tests/qtest/libqos/igb.c:106:5: runt
memcpy to assure
alignment is correct against uint32_t and uint16_t.
Signed-off-by: Nabih Estefan
---
tests/qtest/libqos/igb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/libqos/igb.c b/tests/qtest/libqos/igb.c
index f40c4ec4cd..2e0bb58617 100644
--- a/t
ignment is correct against uint32_t and uint16_t.
Change-Id: Ibd2bc3d870ea37bcbaf2e459806a22ae17464049
Google-Bug-Id: 391659542
Signed-off-by: Nabih Estefan
---
hw/pci/remote_pci.c | 0
tests/qtest/libqos/igb.c | 8 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
create mode 100
d an AST27x0 boot
> > image.
> > Its source code is available at:
> > https://github.com/google/vbootrom
>
> It is not merged yet. Please resend when done and mention the commit id.
>
> Thanks,
>
> C.
>
>
>
>
> >
> > Signed-off-by:
ad of its own if so it
still throws the warning on all new files instead of ignoring it.
Change-Id: Ic2dae14f8cded0dd02d5b231588bd38d8a00e40d
Signed-off-by: Nabih Estefan
---
scripts/checkpatch.pl | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/sc
: Jamin Lin
Reviewed-by: Nabih Estefan
> ---
> tests/functional/test_aarch64_aspeed.py | 28 +
> 1 file changed, 15 insertions(+), 13 deletions(-)
>
> diff --git a/tests/functional/test_aarch64_aspeed.py
> b/tests/functional/test_aarch64_aspeed.py
>
ated in pc-bios/ast27x0_bootrom.bin.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
> ---
> tests/functional/test_aarch64_aspeed.py | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/tests/functional/test_aarch64_aspeed.py
> b/tests/functional/test_aarch64_a
available at:
> https://github.com/google/vbootrom
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
> ---
> MAINTAINERS | 1 +
> pc-bios/README | 6 ++
> pc-bios/ast27x0_bootrom.bin | Bin 0 ->
es.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
> ---
> include/hw/arm/aspeed.h | 1 +
> hw/arm/aspeed.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> ind
y: Jamin Lin
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
> ---
> hw/arm/aspeed_ast27x0.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index dce7255a2c..b05ed75ff4 100644
>
part of
> the
> boot process.
>
> The vbootrom registered in the SoC's address space using the
> ASPEED_DEV_VBOOTROM
> index.
>
> Introduced a "vbootrom_size" attribute in "AspeedSoCClass" to define virtual
> boot ROM size.
>
> Signed-off-by: Ja
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Using the vbootrom image support and the boot ROM binary is
> now passed via the -bios option, using the image located in
> pc-bios/ast27x0_bootrom.bin.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
> -
y region, using the "-bios" command-line option.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
> ---
> include/hw/arm/aspeed.h | 1 +
> hw/arm/aspeed.c | 36
> 2 files changed, 37 inserti
; ROM sizing logic when both SPI boot and vbootrom are used.
>
> Signed-off-by: Jamin Lin
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
> ---
> hw/arm/aspeed.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspe
xit(1);
> > > > > +}
> > > > > +
> > > > > +ret = load_image_mr(filename, &soc->vbootrom);
> > > > > +if (ret < 0) {
> > > > > +error_report("Failed to load vbootrom image '%s'", filename);
> > > > > +exit(1);
> > > > > +}
> > > > > +}
> > > > > +
> > > > > void aspeed_board_init_flashes(AspeedSMCState *s, const char
> > > > *flashtype,
> > > > > unsigned int count, int
> > > > unit0)
> > > > > {
> > > > > @@ -483,6 +510,11 @@ static void aspeed_machine_init(MachineState
> > > > *machine)
> > > > > }
> > > > > }
> > > > >
> > > > > +if (amc->vbootrom) {
> > > > > +rom_size = memory_region_size(&bmc->soc->vbootrom);> +
> > > > aspeed_load_vbootrom(machine, rom_size);
> > > > > +}
> > > > > +
> > > >
> > > > Even without a vbootrom file, the machine could boot with '-device
> > > > loader'
> > > > options. We should preserve this way of booting an ast2700-evb machine.
> > > >
> > >
> > > Will support both loader and vbootrom.
> > > Thanks for review and suggestion.
> > >
> > > Jamin
> > > >
> > > > Thanks,
> > > >
> > > > C.
> > > >
> > > >
> > > >
> > > >
> > > > > arm_load_kernel(ARM_CPU(first_cpu), machine,
> > > > &aspeed_board_binfo);
> > > > > }
> > > > >
> > >
> >
> > Also, tested against our custom machine + custom bmc image and the bootrom
> > itself works.
> > I think it might just need that default set.
> >
> > Tested-By: Nabih Estefan
Thanks,
Nabih
count, int
> > unit0)
> > > {
> > > @@ -483,6 +510,11 @@ static void aspeed_machine_init(MachineState
> > *machine)
> > > }
> > > }
> > >
> > > +if (amc->vbootrom) {
> > > +rom_size = memory_region_size(&bmc->soc->vbootrom);> +
> > aspeed_load_vbootrom(machine, rom_size);
> > > +}
> > > +
> >
> > Even without a vbootrom file, the machine could boot with '-device loader'
> > options. We should preserve this way of booting an ast2700-evb machine.
> >
>
> Will support both loader and vbootrom.
> Thanks for review and suggestion.
>
> Jamin
> >
> > Thanks,
> >
> > C.
> >
> >
> >
> >
> > > arm_load_kernel(ARM_CPU(first_cpu), machine,
> > &aspeed_board_binfo);
> > > }
> > >
>
Also, tested against our custom machine + custom bmc image and the
bootrom itself works.
I think it might just need that default set.
Tested-By: Nabih Estefan
space of the PCIe Root Port, so it's not an issue
with my device specifically, it seems to be more overarching.
Is this a known limitation of the q35 machine? Is there a way I can
get around this to declare the devices properly?
Thank you!
Nabih Estefan
It already got applied, so idk how worthwhile it is, but for
what it's worth: I was just able to test this whole patchset with our
custom A1 machine + custom A1 image!
I'll keep an eye out on future AST27x0 patches that we can help test
so I can test them earlier in the revision process.
Thank yo
, Mar 6, 2025 at 12:05 AM Cédric Le Goater wrote:
>
> Nabih,
>
> On 3/6/25 01:04, Nabih Estefan wrote:
> >> Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
> >> is done, therefore skipping the u-boot-spl dram_init() process.
> >>
> &g
t;
> Signed-off-by: Jamin Lin
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Thanks,
Nabih
> ---
> hw/arm/aspeed_ast27x0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index
the SCU hw-strap1 register, while hw-strap2 is
> assigned to the SCUIO and sets the value in the SCUIO hw-strap1 register.
>
> Signed-off-by: Jamin Lin
Tested-by: Nabih Estefan
Thanks,
Nabih
> ---
> hw/arm/aspeed_ast27x0.c | 11 +--
> 1 file changed, 9 insertions(+),
cu_reset" function to set the value of
> "s->hw_strap1"
> in both the SCU and SCUIO hw-strap1 registers.
>
> Signed-off-by: Jamin Lin
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Thanks,
Nabih
> ---
> hw/misc/aspeed_scu.c | 3 +--
>
ned-off-by: Jamin Lin
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Thanks,
Nabih
> ---
> hw/arm/aspeed.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 98bf071139..c6c18596d6 100644
> ---
of 0x06010103.
>
> Reference:
> https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/arm/mach-aspeed/ast2700/cpu-info.c
>
> Signed-off-by: Jamin Lin
Tested-by: Nabih Estefan
Thanks,
Nabih
> ---
> hw/misc/aspeed_scu.c | 3 +--
> 1 file change
> Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
> is done, therefore skipping the u-boot-spl dram_init() process.
>
> Signed-off-by: Jamin Lin
> Signed-off-by: Troy Lee
> Reviewed-by: Cédric Le Goater
Tested-by: Nabih Estefan
Thanks,
Nabih
not actually
fixing it. We shouldn't actually merge this, we should instead fix
https://lists.gnu.org/archive/html/qemu-s390x/2024-09/msg00264.html.
- Nabih
On Mon, Dec 16, 2024 at 5:40 AM Peter Maydell wrote:
>
> On Fri, 13 Dec 2024 at 22:40, Nabih Estefan wrote:
&g
8858371259250
[R +0.027812] readl 0x482c
sse_timer_read SSE system timer read: offset 0x2c data 0x5 size 4
[S +0.027819] OK 0x0005
ok 3 /arm/sse-timer/timer-scale-change
# End of sse-timer tests
# End of arm tests
[I +0.028089] CLOSED
On Fri, Dec 13, 2024 at 2:40 PM Nabih Estefan
g and thus letting the timer and
counter run as expected
Also renaming the reset_counter_and_timer function since it now also
affects the watchdog.
To reproduce the failure at HEAD:
./configure --target-list=arm-softmmu
make -j check-report-qtest-arm.junit.xml
Signed-off-by: Nabih Estefan
Test
>From what I can tell this is the same issue Thomas was looking at yes.
I saw the failure on the master branch at the v9.2.0 tag (ae35f033) and just
re-tested it against (83aaec1d) and still see it. I haven't seen it be an
intermittent failure, it has failed 100% of the time that I have tested it
affects the watchdog.
To reproduce the failure at HEAD:
./configure --target-list=arm-softmmu
make -j check-report-qtest-arm.junit.xml
Signed-off-by: Nabih Estefan
---
scripts/meson-buildoptions.sh.tmp | 0
tests/qtest/sse-timer-test.c | 19 ++-
2 files changed, 14
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
There is an extra `buf=` set that is not used by npcm-gmac. Remove it
for coverity to be happy.
Signed-off-by: Nabih Estefan
---
hw/net/npcm_gmac.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
index 1b71e2526e..b397fd5064 100644
--- a/hw/net
Friendly ping on review for this patchset!
It's been ~2 weeks since it was sent out, please let us know if
there's any changes that should be done to upstream it!
Thanks,
Nabih Estefan
Nabih Estefan (he/him) | Software Engineer |
nabiheste...@google.com | 857-308-9574
On Wed, Fe
GUID will be part of the Namespace Identification Descriptor
list and the Identify Namespace data.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
Reviewed-by: Klaus Jensen
---
docs/system/devices/nvme.rst | 7 ++
hw/nvme/ctrl.c | 12 +++
hw/nvme/meson.build
GUID will be part of the Namespace Identification Descriptor
list and the Identify Namespace data.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
docs/system/devices/nvme.rst | 7 ++
hw/nvme/ctrl.c | 12 +++
hw/nvme/meson.build | 2
Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
hw/intc/arm_gicv3_its_kvm.c| 2 +-
include/hw/intc/arm_gicv3_its_common.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 3befc960db..4eaf1cfcad 100644
From: Roque Arcudia Hernandez
This is trying to achieve 2 things: To be able to redefine the send_msi in a
derived class of arm_gicv3_its and/or to expose a method call interface to
inject interrupts from another device.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
This patch series modifies the ARM GICv3 ITS to use the already existing
send_msi virtual function when writing the GITS_TRANSLATER in order to be able
to modify the final DeviceID to an implementation specific version that requires
extra information besides the BDF that comes in the requester_id.
This patch series modifies the ARM SMMUv3 to be able to work with an
implementation specific StreamID that does not match exactly the PCIe BDF.
The way to achieve this is by converting the smmu_get_sid and smmu_iommu_mr
functions to virtual functions that can be overridden by inheritance, making
su
and
redefining the value of SMMU_IDR1.SIDSIZE because the check is hardcoded to the
constant SMMU_IDR1_SIDSIZE rather than the register value.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
hw/arm/smmuv3.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
constructed via inheritance. The default
implementation of these functions will match the current ones where the BDF is
used directly as StreamID.
Signed-off-by: Roque Arcudia Hernandez
Signed-off-by: Nabih Estefan
---
hw/arm/smmu-common.c | 12
include/hw/arm/smmu-common.h | 16
From: Felix Wu
Version 2.1+.
Signed-off-by: Felix Wu
Signed-off-by: Nabih Estefan
---
hw/smbios/smbios.c | 99
include/hw/firmware/smbios.h | 13 +
qemu-options.hx | 3 ++
3 files changed, 115 insertions(+)
diff --git a/hw
This patch series implements SMBIOS type 9 descriptor, system slots.
For each system slot, we can assign one descriptor for it if needed.
In versions later than 2.6, a new PCI device field was added to make sure the
descriptor is associated with a certain device, if provided.
For ease of usage, qem
From: Felix Wu
Signed-off-by: Felix Wu
Signed-off-by: Nabih Estefan
---
hw/smbios/smbios.c | 49 +---
include/hw/firmware/smbios.h | 4 +++
qemu-options.hx | 2 +-
3 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/hw
Fixing the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fixing comments referencing this and values expecting 8xx.
Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
Signed-Off-By: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 4
Accidentally added extra file to v2 that broke email sending (and was
not meant to be upstreamed). Sending our v3 to skip that confusion.
Removing testing for PCS registers since that doesn't exist on 7xx.
Nabih Estefan (1):
tests/qtest: Fixing GMAC test to run in 7xx
tests/qtest/meson.
Removing testing for PCS registers since that doesn't exist on 7xx.
Nabih Estefan (1):
tests/qtest: Fixing GMAC test to run in 7xx
obmc-phosphor-image-gsj.static.mtd | Bin 0 -> 33554432 bytes
tests/qtest/meson.build| 4 +-
tests/qtest/npcm_gmac-test.c
Removing testing for PCS registers since that doesn't exist on 7xx.
Nabih Estefan (1):
tests/qtest: Fixing GMAC test to run in 7xx
obmc-phosphor-image-gsj.static.mtd | Bin 0 -> 33554432 bytes
tests/qtest/meson.build| 4 +-
tests/qtest/npcm_gmac-test.c
Nabih Estefan (1):
tests/qtest: Fixing GMAC test to run in 7xx
tests/qtest/meson.build | 4 ++--
tests/qtest/npcm_gmac-test.c | 12 ++--
2 files changed, 4 insertions(+), 12 deletions(-)
--
2.43.0.594.gd9cf4e227d-goog
Fixing the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fixing comments referencing this and values expecting 8xx.
Change-Id: I07b91e8be473e6a1ece65a2202608b52ed4025b8
Signed-Off-By: Nabih Estefan
---
tests/qtest/meson.build | 4 ++--
tests/qtest/npcm_gmac
[Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan Diaz
Reviewed-by: Tyrone Ting
---
hw/net/meson.build
From: Nabih Estefan Diaz
[Changes since v15]
Dropped PCI MBox patches. They were presenting a lot of problems with
endianness and are not directly related to the GMAC. Breaking them apart to
debug separately and let the GMAC itself be upstreamed faster.
[Changes since v14]
Expanded comment
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
wit
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 37 +++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 37 insertions(+), 2
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
From: Nabih Estefan Diaz
[Changes since v15]
Dropped PCI MBox patches. They were presenting a lot of problems with
endianness and are not directly related to the GMAC. Breaking them apart to
debug separately and let the GMAC itself be upstreamed faster.
[Changes since v14]
Expanded comment
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
wit
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 37 +++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 37 insertions(+), 2
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest
[Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan Diaz
Reviewed-by: Tyrone Ting
---
hw/net/meson.build
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC
[Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan Diaz
Reviewed-by: Tyrone Ting
---
hw/net/meson.build
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
wit
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
with the core CPU is emulated via a chardev and
will be in a follow-up patch.
This patch also adds documentation on the PCIe Protocol used
by the chardev device.
Change-Id: Iaca22f81c4526927d437aa367079ed038faf43f2
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 17
From: Nabih Estefan Diaz
[Changes since v14]
Expanded comment on chardev device and fixed comment formatting
[Changes since v13]
Added a couple clarifying comments and documentation about chardev
device expected protocol for ease of review.
[Changes since v12]
Fix errors found when testing in
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 17
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
wit
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2
with the core CPU is emulated via a chardev and
will be in a follow-up patch.
Change-Id: Iaca22f81c4526927d437aa367079ed038faf43f2
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/misc/meson.build| 1 +
hw/misc/npcm7xx_pci_mbox.c | 333
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC
From: Nabih Estefan Diaz
[Changes since v13]
Added a couple clarifying comments and documentation about chardev
device expected protocol for ease of review.
[Changes since v12]
Fix errors found when testing in big-endian host.
[Changes since v11]
Branch couldn't be merged with master be
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest
[Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan Diaz
Reviewed-by: Tyrone Ting
---
hw/net/meson.build
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 17
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