[PATCH v1] target/riscv: add support for RV64 Xiangshan Nanhu CPU

Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/overview Signed-off-by: MollyChen --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 29

[PATCH RESEND v1] target/riscv: add support for RV64 Xiangshan Nanhu CPU

Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/overview Signed-off-by: MollyChen --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 29

[PATCH v1] Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/ove

Signed-off-by: MollyChen --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 29 + 2 files changed, 30 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 62115375cd..8f6fac463c 100644 --- a/target/riscv/cpu-qom.h +++ b/target