This mirrors the interleaving support already in place in
pflash_cfi01.c, using the max_device_width and device_width properties.
Signed-off-by: Mike Nawrocki
---
hw/block/pflash_cfi02.c | 244 +---
1 file changed, 209 insertions(+), 35 deletions
Signed-off-by: Mike Nawrocki
---
hw/block/pflash_cfi02.c | 143 ++--
1 file changed, 102 insertions(+), 41 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index a81df913f6..29eb0429a3 100644
--- a/hw/block/pflash_cfi02.c
Signed-off-by: Mike Nawrocki
---
hw/block/pflash_cfi02.c | 97 +
1 file changed, 18 insertions(+), 79 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index c81ddd3a99..a81df913f6 100644
--- a/hw/block/pflash_cfi02.c
he same interface as pflash_cfi01.c. Much
of the code was taken and adapted from that file.
Version 3 of the patch splits the patch set into distinct patches based on the
modified functionality.
Mike Nawrocki (3):
Switch AMD CFI flash to use new MMIO API
Enable 8-byte wide access to AMD CFI devices
This adds 8-byte wide access support to AMD CFI flash devices.
Additionally, it migrates the MMIO operations from old_mmio to the new
API. Finally, it mirrors the interleaving support already in place in
pflash_cfi01.c, using the max_device_width and device_width properties.
Signed-off-by: Mike
he same interface as pflash_cfi01.c. Much
of the code was taken and adapted from that file.
Version 1 of the patch set changed the flash register function (and all
usages), version 2 localizes changes to the pflash_cfi02.c file.
Mike Nawrocki (1):
Add 8-byte access, interleaving to AMD CF
Adds a new PCI ID for the i82559a (0x8086 0x1030) interface. The
"x-use-alt-device-id" property controls whether this new ID is to be
used, and is true by default, and set to false in a compat entry.
Signed-off-by: Mike Nawrocki
---
hw/net/eepro100.c| 13 +
include/h
x-use-alternate-device-id"
property. This property is set to the compat value of false in
"hw/include/compat.h"
Mike Nawrocki (2):
Fix eepro100 simple transmission mode
Add new PCI ID for i82559a
hw/net/eepro100.c| 31 ---
include/hw/compat.h | 4 +
The simple transmission mode was treating the area immediately after the
transmit command block (TCB) as if it were a transmit buffer descriptor,
when in reality it is simply the packet data. This change simply copies
the data following the TCB into the packet buffer.
Signed-off-by: Mike Nawrocki
Adds a new PCI ID for the i82559a (0x8086 0x1030) interface. Enables
this ID with a new property "use-alt-device-id" to preserve
compatibility.
Signed-off-by: Mike Nawrocki
---
hw/net/eepro100.c| 12
include/hw/pci/pci.h | 1 +
qemu-options.hx | 2 +-
3 files c
e-alt-device-id".
Mike Nawrocki (2):
Fix eepro100 simple transmission mode
Add new PCI ID for i82559a
hw/net/eepro100.c| 30 +++---
include/hw/pci/pci.h | 1 +
qemu-options.hx | 2 +-
3 files changed, 17 insertions(+), 16 deletions(-)
--
2.14.2
The simple transmission mode was treating the area immediately after the
transmit command block (TCB) as if it were a transmit buffer descriptor,
when in reality it is simply the packet data. This change simply copies
the data following the TCB into the packet buffer.
Signed-off-by: Mike Nawrocki
Some drivers for the PPMC7400 PowerPC evaluation board accesses the
serial registers through the floating point unit (stfd/ldfd), which is
an 8-byte wide access. This patch enables that behavior.
Signed-off-by: Mike Nawrocki
---
hw/char/serial.c | 8 +++-
1 file changed, 7 insertions(+), 1
Signed-off-by: Mike Nawrocki
---
hw/net/eepro100.c| 2 +-
hw/pci/pci.c | 2 ++
include/hw/pci/pci.h | 1 +
qemu-options.hx | 2 +-
4 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index 91dd058010..2c7c5cdeb9 100644
--- a/hw
The simple transmission mode was treating the area immediately after the
transmit command block (TCB) as if it were a transmit buffer descriptor,
when in reality it is simply the packet data. This change simply copies
the data following the TCB into the packet buffer.
Signed-off-by: Mike Nawrocki
This patch set does two things. First, it fixes the simple transmission mode
for the eepro100 chipset. Second, it adds and uses the PCI ID for the i82559
chipset, and enables selection of this chipset.
Mike Nawrocki (2):
Fix eepro100 simple transmission mode
Add i82559a eepro100 interface
This adds 8-byte wide access support to AMD CFI flash devices.
Additionally, it migrates the MMIO operations from old_mmio to the new
API.
Signed-off-by: Mike Nawrocki
---
hw/block/pflash_cfi02.c | 172 +++-
1 file changed, 81 insertions(+), 91
fy the AMD device array.
Issuing commands to individual members of the flash array is not
supported.
Signed-off-by: Mike Nawrocki
---
hw/arm/digic_boards.c| 2 +-
hw/arm/musicpal.c| 4 ++--
hw/arm/xilinx_zynq.c | 2 +-
hw/block/pflash_cfi
all "chips"
simultaneously. See the example in the second patch for more details. This
behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
Mike Nawrocki (2):
Add 8-byte access to AMD CFI devices
Add support for flash interleaving of AMD chips
hw/arm/digic_boards.c
Some drivers for the PPMC7400 PowerPC evaluation board accesses the
serial registers through the floating point unit (stfd/ldfd), which is
an 8-byte wide access. This patch enables that behavior.
Signed-off-by: Mike Nawrocki
---
hw/char/serial.c | 8 +++-
1 file changed, 7 insertions(+), 1
Signed-off-by: Mike Nawrocki
Sorry, I was only testing against the ppc-softmmu and ppc64-softmmu targets.
I've now validated that this compiles against the following targets:
ppc-softmmu,ppc64-softmmu,ppcemb-softmmu,s390x-softmmu,sh4-softmmu,ppc-linux-user,ppc64-linux-user,ppc64abi32-linux
Signed-off-by: Mike Nawrocki
I've rebased my branch on master and regenerated the patch.
I've run the patch through checkstyle.pl and it reported no issues, whitespace
or otherwise. I suspect that Outlook was messing with my formatting, so let's
give git send-email a go. Ple
22 matches
Mail list logo
