On 5/15/2025 7:12 PM, Nicholas Piggin wrote:
On Mon May 12, 2025 at 1:10 PM AEST, Nicholas Piggin wrote:
From: Glenn Miles
The current xive algorithm for finding a matching group vCPU
target always uses the first vCPU found. And, since it always
starts the search with thread 0 of a core, th
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 24
hw/intc/xive2.c | 28 ++
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
After pulling the pool context, if a pool irq had been presented and
was cleared in the process, there could be a pending irq in phys that
should be presented. Process the phys irq ring after pulling pool ring
to catch this case and avoid losing irq
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
When pushing a context, the lower-level context becomes valid if it
had V=1, and so on. Iterate lower level contexts and send them
pending interrupts if they become enabled.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Implement pool context push TIMA op.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 4
hw/intc/xive2.c| 50 --
include/hw/ppc/xive2.
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Implement set LGS for the POOL ring.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index dc64edf13d..807
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Implement the phys (aka hard) VP push. PowerVM uses this operation.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c| 11 +++
include/hw/ppc/xive2.h
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
xive2 must take into account redistribution of group interrupts if
the VP directed priority exceeds the group interrupt priority after
this operation. The xive1 code is not group aware so implement this
for xive2.
Reviewed-by: Michael Kowal
Than
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Certain TIMA operations should only be performed when a ring is valid,
others when the ring is invalid, and they are considered undefined if
used incorrectly. Add checks for this condition.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by:
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
When pushing a context, any presented group interrupt should be
redistributed before processing pending interrupts to present
highest priority.
This can occur when pushing the POOL ring when the valid PHYS
ring has a group interrupt presented, beca
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
When the pool context is pulled, the shared pool/phys signal is
reset, which loses the qemu irq if a phys interrupt was presented.
Only reset the signal if a poll irq was presented.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nichol
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
In preparation to implement POOL context push, add support for POOL
NVP context save/restore.
The NVP p bit is defined in the spec as follows:
If TRUE, the CPPR of a Pool VP in the NVP is updated during store of
the context with the CPPR
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
OS-push operation must re-present pending interrupts. Use the
newly created xive2_tctx_process_pending() function instead of
duplicating the logic.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c |
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Add some assertions to try to ensure presented group interrupts do
not get lost without being redistributed, if they become precluded
by CPPR or preempted by a higher priority interrupt.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Ni
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
When CPPR priority is decreased, pending interrupts do not need to be
re-checked if one is already presented because by definition that will
be the highest priority.
This prevents a presented group interrupt from being lost.
Reviewed-by: Michael
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
The second part of the set CPPR operation is to process (or re-present)
any pending interrupts after CPPR is adjusted.
Split this presentation processing out into a standalone function that
can be used in other places.
Reviewed-by: Michael Kowal
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update()
causes VP-directed (group==0) interrupt to be presented in PIPR and NSR
despite being a lower priority than the currently presented group
interrupt.
This must not happen. The IPB
On 5/14/2025 3:10 PM, Mike Kowal wrote:
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Why is this a
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).
Reviewed-by: Michael Kowal
Thanks, M
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
...needs to be...
lowered together and "just in case" lowering should be avoided (it could
mask
I think
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
The tctx "signaling" registers (PIPR, CPPR, NSR) raise an interrupt on
the target CPU thread. The POOL and PHYS rings both raise hypervisor
interrupts, so they both share one set of signaling registers in the
PHYS ring. The PHYS NSR register contain
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Further split xive_tctx_pipr_update() by splitting out a new function
that is used to re-compute the PIPR from IPB. This is generally only
used with XIVE1, because group interrputs require more logic.
Previous upstreaming was focused only on XIVE
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Why is this a separate commit fro 30? The change here does
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
A group interrupt that gets preempted by a higher priority interrupt
delivery must be redistributed otherwise it would get lost.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 14 --
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Have the match_nvt method only perform a TCTX match but don't present
the interrupt, the caller presents. This has no functional change, but
allows for more complicated presentation logic after matching.
I always found the count meaning less sinc
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
When disabling (pulling) an xive interrupt context, we need
to redistribute any active group interrupts to other threads
that can handle the interrupt if possible. This support had
already been added for the OS context but had n
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Change pregs to pool_regs, for clarity.
Reviewed-by: Michael Kowal
Thanks, MAK
[npiggin: split from larger patch]
Signed-off-by: Glenn Miles
---
hw/intc/xive2.c | 11 +--
1 file changed, 5 insertions(+), 6 dele
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Add support for redistributing a presented group interrupt if it
is precluded as a result of changing the CPPR value. Without this,
group interrupts can be lost.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Glenn
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Booting AIX in a PowerVM partition requires the use of the "Acknowledge
O/S Interrupt to even O/S reporting line" special operation provided by
the IBM XIVE interrupt controller. This operation is invoked by writing
a byte (data
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Add more tracing around notification, redistribution, and escalation.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Glenn Miles
---
hw/intc/trace-events | 6 ++
hw/intc/xive.c | 3 +++
hw/intc/xive
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Adds support for extracting additional configuration flags from
the XIVE configuration register that are needed for redistribution
of group interrupts.
Reviewed-by: Michael Kowal
Thanks, MAK
Signed-off-by: Glenn Miles
--
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Michael Kowal
Writes to the Flush Control registers were logged as invalid
when they are allowed. Clearing the unsupported want_cache_disable
feature is supported, so don't log an error in that case.
Reviewed-by: Michael Kowal
Thanks MA
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Michael Kowal
This can make it easier to see what the target system is trying to
do.
Reviewed-by: Michael Kowal
Thanks MAK
[npiggin: split from larger patch]
Signed-off-by: Michael Kowal
---
hw/intc/pnv_xive2.c | 24 ++
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
register, so don't clear it on read.
Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
at write already.
Reviewed-by: Michael Kowal
Thanks MAK
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Have xive_tctx_accept clear NSR in one shot rather than masking out bits
as they are tested, which makes it clear it's reset to 0, and does not
have a partial NSR value in the register.
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 6 ++---
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Rather than functions to return masks to test NSR bits, have functions
to test those bits directly. This should be no functional change, it
just makes the code more readable.
Reviewed-by: Michael Kowal
Thanks MAK
Signed-off-by: Nicholas Pigg
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
This improves the implementation of pulling pool and phys contexts in
XIVE1, by following closer the OS pulling code.
In particular, the old ring data is returned rather than the modified,
and irq signals are reset on pull.
Reviewed-by: Michael K
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
Add support for XIVE ESB Interrupt Escalation.
Reviewed-by: Michael Kowal
Thanks MAK
Suggested-by: Michael Kowal
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles
---
hw/intc/x
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
If CPPR is lowered to preclude the pending interrupt, NSR should be
cleared and the qemu_irq should be lowered. This avoids some cases
of supurious interrupts.
Reviewed-by: Michael Kowal
Thanks MAK
Signed-off-by: Nicholas Piggin
---
hw/in
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
The group interrupt delivery flow selects the group backlog scan if
LSMFB < IPB, but that scan may find an interrupt with a priority >=
IPB. In that case, the VP-direct interrupt should be chosen. This
extends to selecting the lowest prio between PO
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Group interrupts should not be taken from the backlog and presented
if they are precluded by CPPR.
Reviewed-by: Michael Kowal
Thanks MAK
Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
context")
Signed-off-by: Nichol
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
According to the XIVE spec, updating the CPPR should also update the
PIPR. The final value of the PIPR depends on other factors, but it
should never be set to a value that is above the CPPR.
Also added support for redistributing
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
A problem was seen where uart interrupts would be lost resulting in the
console hanging. Traces showed that a lower priority interrupt was
preempting a higher priority interrupt, which would result in the higher
priority interrup
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
The current xive algorithm for finding a matching group vCPU
target always uses the first vCPU found. And, since it always
starts the search with thread 0 of a core, thread 0 is almost
always used to handle group interrupts. Th
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Michael Kowal
When the END Event Queue wraps the END EQ Generation bit is flipped and the
Generation Flipped bit is set to one. On a END cache Watch read operation,
the Generation Flipped bit needs to be reset.
While debugging an error mod
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Test that the NSR exception bit field is equal to the pool ring value,
rather than any common bits set, which is more correct (although there
is no practical bug because the LSI NSR type is not implemented and
POOL/PHYS NSR are encoded with exclusiv
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Pushing a context and loading IPB from NVP is defined to merge ('or')
that IPB into the TIMA IPB register. PIPR should therefore be calculated
based on the final IPB value, not just the NVP value.
Reviewed-by: Michael Kowal
Thanks MAK
Fixes: 9d2
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Michael Kowal
In a multi chip environment there will be remote/forwarded VSDs. The check
to find a matching INT controller (XIVE) of the remote block number was
checking the INTs chip number. Block numbers are not tied to a chip number.
Th
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
From: Glenn Miles
The queue size of an Event Notification Descriptor (END)
is determined by the 'cl' and QsZ fields of the END.
If the cl field is 1, then the queue size (in bytes) will
be the size of a cache line 128B * 2^QsZ and QsZ is limited
t
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Report access size in XIVE TM operation error logs.
Reviewed-by: Michael Kowal
Thanks MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/xive.c b/hw/i
On 5/11/2025 10:10 PM, Nicholas Piggin wrote:
Typo, IBP should be IPB.
Reviewed-by: Michael Kowal
Thanks MAK
Signed-off-by: Nicholas Piggin
---
hw/intc/trace-events | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
On 11/21/2024 4:56 PM, Mike Kowal wrote:
On 11/18/2024 9:22 PM, Nicholas Piggin wrote:
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
From: Frederic Barrat
If an END has the 'i' bit set (ignore), then it targets a group of
VPs. The size of the group depends on the V
On 11/18/2024 11:00 PM, Nicholas Piggin wrote:
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
From: Glenn Miles
END notification processing has an escalation path. The escalation is
not always an END escalation but can be an ESB escalation.
Also added a check for 'resume' proces
On 11/18/2024 10:34 PM, Nicholas Piggin wrote:
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
From: Frederic Barrat
When the hypervisor or OS pushes a new value to the CPPR, if the LSMFB
value is lower than the new CPPR value, there could be a pending group
interrupt in the backlog,
On 11/18/2024 9:22 PM, Nicholas Piggin wrote:
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
From: Frederic Barrat
If an END has the 'i' bit set (ignore), then it targets a group of
VPs. The size of the group depends on the VP index of the target
(first 0 found when looking at the
On 11/18/2024 8:08 PM, Nicholas Piggin wrote:
On Wed Oct 16, 2024 at 7:13 AM AEST, Michael Kowal wrote:
From: Frederic Barrat
The NSR has a (so far unused) grouping level field. When a interrupt
is presented, that field tells the hypervisor or OS if the interrupt
is for an individual VP or f
On 10/16/2024 3:33 AM, Thomas Huth wrote:
On 15/10/2024 23.13, Michael Kowal wrote:
From: Glenn Miles
Added new test for pool interrupts.
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
---
tests/qtest/pnv-xive2-test.c | 77
1 file changed, 77
On 9/18/2024 2:25 PM, Mike Kowal wrote:
On 9/18/2024 10:46 AM, Cédric Le Goater wrote:
Hello, On 9/16/24 20:23, Michael Kowal wrote:
From: Frederic Barrat
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
On 9/18/2024 10:46 AM, Cédric Le Goater wrote:
Hello, On 9/16/24 20:23, Michael Kowal wrote:
From: Frederic Barrat
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
- end of interrupt processing
- Test the Pul
On 9/18/2024 10:05 AM, Thomas Huth wrote:
On 16/09/2024 20.23, Michael Kowal wrote:
From: Frederic Barrat
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
- end of interrupt processing
- Test the Pull Thread
On 9/13/2024 8:10 AM, Cédric Le Goater wrote:
On 9/12/24 22:50, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or
context. Some
of these same functions are being changed to operate on any
ring/context. This will
simplify the next patch sets that are add
On 9/12/2024 1:27 AM, Cédric Le Goater wrote:
On 9/9/24 23:10, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or
context. Some
of these same functions are being changed to operate on any
ring/context. This will
simplify the next patch sets that are addi
On 8/30/2024 3:25 AM, Cédric Le Goater wrote:
On 8/29/24 22:35, Mike Kowal wrote:
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept()
function
instead of the
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept()
function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Did you confirm with th
On 8/29/2024 7:14 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and
instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use so
On 8/29/2024 7:08 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state informat
On 7/16/2024 3:18 PM, Cédric Le Goater wrote:
Hello Mike,
On 7/16/24 21:56, Michael Kowal wrote:
These changes provide enhanced support of the External Interrupt
Virtualization
Engine. The changes are focused on the following areas:
- Cache Watch, Cache Flush and Sync Injection
- Virtua
On 7/16/2024 10:46 AM, Mike Kowal wrote:
On 7/16/2024 2:29 AM, Cédric Le Goater wrote:
On 7/15/24 20:33, Michael Kowal wrote:
From: Frederic Barrat
The cache watch facility uses the same register interface to handle
entries in the NVP, NVG and NVC tables. A bit-field in the 'w
On 7/16/2024 10:32 AM, Mike Kowal wrote:
On 7/16/2024 2:28 AM, Cédric Le Goater wrote:
On 7/15/24 20:33, Michael Kowal wrote:
From: Frederic Barrat
XIVE offers a 'cache watch facility', which allows software to
read/update
a potentially cached table entry with no software loc
On 7/16/2024 2:29 AM, Cédric Le Goater wrote:
On 7/15/24 20:33, Michael Kowal wrote:
From: Frederic Barrat
The cache watch facility uses the same register interface to handle
entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX
specification' register tells the table type. So f
On 7/16/2024 2:28 AM, Cédric Le Goater wrote:
On 7/15/24 20:33, Michael Kowal wrote:
From: Frederic Barrat
XIVE offers a 'cache watch facility', which allows software to
read/update
a potentially cached table entry with no software lock. There's one such
facility in the Virtualization Cont
Hello Cedric,
This patch will be split into 5 patches to ease the review. I also
acknowledge most of your other comments.
Can you elaborate on the gic_get_current_cpu() comment? Did you want me
to use that method name to get a the current CPU? Also, is this
something that you think needs
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