On 09/06/2018 08:44 AM, Peter Maydell wrote:
On 6 September 2018 at 16:07, Michael Eager wrote:
Any comments?
I'd quite like to hear from somebody more familiar with the
readconfig/writeconfig stuff than me about whether this
very riscv-centric approach makes sense and fits with ho
Any comments?
On 08/30/2018 09:22 AM, Michael Eager wrote:
Corrected patch attached.
On 08/29/2018 05:48 PM, Michael Eager wrote:
Whoops. I just noticed that this patch is against the riscv-qemu
repo on github, not the qemu.org repo. I will rework it for the
qemu.org repo. Meanwhile, I
Corrected patch attached.
On 08/29/2018 05:48 PM, Michael Eager wrote:
Whoops. I just noticed that this patch is against the riscv-qemu
repo on github, not the qemu.org repo. I will rework it for the
qemu.org repo. Meanwhile, I welcome any comments.
On 08/29/2018 05:21 PM, Michael Eager
Whoops. I just noticed that this patch is against the riscv-qemu
repo on github, not the qemu.org repo. I will rework it for the
qemu.org repo. Meanwhile, I welcome any comments.
On 08/29/2018 05:21 PM, Michael Eager wrote:
Memory parameters for RISC-V boards can be read from a
= "0xc00"
plic-size= "0x400"
uart0-base = "0x1000"
uart0-size = "0x100"
virtio-base = "0x10001000"
virtio-size = "0x1000"
dram-base= "0x8000"
dram-size= "0
omeone offer me some clarifications on how warping the icount clock
is done, or better yet send me (or tell me where to find) a working test
case using QEMU and -icount which warps the icount timer when all vCPUs
are idle?
Thanks in advance.
--
Michael Eagerea...@eagerm.com
1960 Park Blvd., Palo Alto, CA 94306
On 05/02/2017 12:59 AM, Paolo Bonzini wrote:
On 01/05/2017 03:57, Michael Eager wrote:
I'm seeing incorrect values when there is a write to a memory-mapped I/O
device when icount is set. What I see happening is that a TB with ~20
instructions is executed which contains a write to the
ng, long time. Has anyone noticed this
problem in the past?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
ng, long time. Has anyone noticed this
problem in the past?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 12/12/2012 06:25 AM, Andreas Färber wrote:
Hi,
Am 11.12.2012 19:40, schrieb Michael Eager:
Is there any internal documentation for QEMU?
I'm adding support for a new processor. I'm currently
adding semihosting support and a new command line option.
I find that I'm r
On 12/12/2012 05:39 AM, Stefan Hajnoczi wrote:
On Tue, Dec 11, 2012 at 10:40:45AM -0800, Michael Eager wrote:
Is there any internal documentation for QEMU?
Nothing up-to-date and complete.
I'm adding support for a new processor. I'm currently
adding semihosting support and a n
various targets are implemented.
Is there a better way?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
sc patchset [1], it's a relative
> new added guest support.
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2012-07/msg02567.html
Thanks.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 08/25/2012 05:57 AM, 陳韋任 (Wei-Ren Chen) wrote:
On Fri, Aug 24, 2012 at 05:46:43PM -0700, Michael Eager wrote:
Is there a description of how to add a new processor architecture
to QEMU? I looked at the Wiki and at the QEMU-Buch, but there
doesn't seem to be anything on topic.
Lo
Is there a description of how to add a new processor architecture
to QEMU? I looked at the Wiki and at the QEMU-Buch, but there
doesn't seem to be anything on topic.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 07/19/2012 08:59 AM, Laurent Desnogues wrote:
On Thu, Jul 19, 2012 at 5:29 PM, Michael Eager wrote:
I'm interested in using QEMU to test gcc for a processor.
This is a hard-metal target -- there is no operating system.
Can anyone make suggestions on how to do this?
You could look a
I'm interested in using QEMU to test gcc for a processor.
This is a hard-metal target -- there is no operating system.
Can anyone make suggestions on how to do this?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
On 05/23/2012 08:59 AM, Stefan Weil wrote:
Am 23.05.2012 16:37, schrieb Michael Eager:
On 05/22/2012 11:18 PM, 陳韋任 wrote:
I'm investigating adding a new target architecture
to QEMU. Are there documents, how-to's, or other
guidance on how to approach this? Or any advice?
I noticed
mple. Otherwise, looks at tcg/xxx/*.
The term "target" could be a little MISLEADING here. :)
I'm interested in adding a new emulated architecture,
not a new host. So adding a new target- sounds
like the plan.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
ions under tcg for arm and mips. I
noticed that target-microblaze exists, but there is
no microblaze directory under tcg. What does this
mean?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
Works for me.
On 11/07/2011 03:05 PM, Edgar E. Iglesias wrote:
On Mon, Nov 07, 2011 at 02:46:47PM -0800, Michael Eager wrote:
The declaration of clk_setup is missing in
qemu/hw/virtex_ml507.c:
static void virtex_init(ram_addr_t ram_size,
const char *boot_device
_uc.c, there
is a decl:
clk_setup_t clk_setup[PPC405EP_CLK_NB];
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
er/source/qemu/build/i386-softmmu'
make: *** [subdir-i386-softmmu] Error
Is there a fix for this problem?
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
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