Hi All,
On 6/23/25 08:47, Michael Clark wrote:
[snipped]
btw this started as a sketch in a gist in June 20th of last year:
https://gist.github.com/michaeljclark/8f9b81e5e40488035dc252c9da3ecc2e
# the glyph architecture
current: https://metaparadigm.com/~mclark/glyph.pdf
latest: https
Hi QEMU Folks,
# background
I'm sending this out here because if I was a QEMU developer I'd like
to read about this, as it is informed by working on QEMU and other
simulators and emulators. this work is by-no-means complete. in fact,
it is just the beginning, but there is enough present for feed
Hi QEMU Folks,
# background
I'm sending this out here because if I was a QEMU developer I'd like
to read about this, as it is informed by working on QEMU and other
simulators and emulators. this work is by-no-means complete. in fact,
it is just the beginning, but there is enough present for feed
license:
- https://github.com/michaeljclark/x86
Signed-off-by: Michael Clark
---
docs/x86-metadata.txt | 303 ++
1 file changed, 303 insertions(+)
create mode 100644 docs/x86-metadata.txt
diff --git a/docs/x86-metadata.txt b/docs/x86-metadata.txt
new file
that encodes operand field order
- x86 register enum and string table
- x86 opcode enum and string table
this code is from an external project with an MIT license:
- https://github.com/michaeljclark/x86
Signed-off-by: Michael Clark
---
scripts/x86-tablegen.py | 695
e and operand documentation.
- addressed non-whitespace related checkpatch.pl warnings.
Michael Clark (4):
x86-disas: add x86-mini instruction set metadata
x86-disas: add x86-mini metadata documentation
x86-disas: add x86-mini metadata tablegen script
x86-disas: add x86-mini disassembler implement
On 5/14/25 21:33, Daniel P. Berrangé wrote:
On Wed, May 14, 2025 at 09:23:58PM +1200, Michael Clark wrote:
On 5/14/25 20:17, Daniel P. Berrangé wrote:
On Wed, May 14, 2025 at 07:39:27PM +1200, Michael Clark wrote:
diff --git a/disas/x86-core.c b/disas/x86-core.c
new file mode 100644
index
On 5/14/25 22:25, Philippe Mathieu-Daudé wrote:
Hi Michael,
Minor comments inline.
On 14/5/25 09:39, Michael Clark wrote:
[snipped]
+
+static void x86_print_row(size_t count, x86_table_col *cols)
+{
+ printf("|");
+ for (size_t i = 0; i < count; i++) {
+ printf(&q
On 5/14/25 20:17, Daniel P. Berrangé wrote:
On Wed, May 14, 2025 at 07:39:27PM +1200, Michael Clark wrote:
diff --git a/disas/x86-core.c b/disas/x86-core.c
new file mode 100644
index ..c4f7034e3420
--- /dev/null
+++ b/disas/x86-core.c
@@ -0,0 +1,2716 @@
+/*
+ * Copyright (c) 2024
instruction stream into
two streams, one for instructions and and one for constants:
- latest: https://metaparadigm.com/~mclark/glyph.pdf
- current: https://metaparadigm.com/~mclark/glyph-20250512.pdf
- emulator: https://github.com/michaeljclark/glyph
Michael.
On 5/14/25 19:39, Michael Clark wrote:
a
add detailed information on the instruction opcode encoding
format for LEX/VEX/EVEX prefix, map and opcode encoding, the
operand encoding format, the field order encoding format and
notes on instruction synthesis for parameterized opcodes.
Signed-off-by: Michael Clark
---
docs/x86-metadata.txt
x86 metadata opcode and operand documentation.
- addressed non-whitespace related checkpatch.pl warnings.
Michael Clark (4):
x86-disas: add x86-mini instruction set metadata
x86-disas: add x86-mini metadata documentation
x86-disas: add x86-mini metadata tablegen script
x86-disas: add x86-mini
that encodes operand field order
- x86 register enum and string table
- x86 opcode enum and string table
Signed-off-by: Michael Clark
---
scripts/x86-tablegen.py | 695
1 file changed, 695 insertions(+)
create mode 100755 scripts/x86-tablegen.py
diff
On 2/16/25 06:58, Richard Henderson wrote:
the label member is merely a pointer to the instruction text to
be updated with the relative address of the constant, the primary
data is the constant data pool at the end of translation blocks.
this relates more closely to .data sections in offline co
On 2/16/25 12:41, Richard Henderson wrote:
I don't think this is a good change to make.
fixing varargs codegen in GCC/Clang would be a good change. count
based varargs can be reasoned about statically relatively easily. what
is it like with an explicit inline as opposed to just static?
Inli
On 2/16/25 09:24, Michael Clark wrote:
I actually have a VM in mind that has a constant stream with it's own
counter that branches called IB (immediate base). IB is set in call
procedure and we pack a vector into the link register with the relative
offset of the program counter and imme
On 2/16/25 10:50, Richard Henderson wrote:
On 2/15/25 12:24, Michael Clark wrote:
Why? varargs generally produces horrible code.
The split between alloc and insert was intentional to avoid this.
it's pretty good code on SysV because it goes via registers except for
perhaps new_pool_l8
On 2/16/25 06:58, Richard Henderson wrote:
On 2/14/25 18:11, Michael Clark wrote:
the intent of this patch is more conventional nomenclature
but the constant pool data code is also simplified a little.
- merge new_pool_{alloc,insert} -> new_pool_data.
- rename TCGLabelPoolData -> T
list with varargs to allocate, copy, and
insert constant data items to simplify new_pool_label et al.
a successive step would be to collapse callers into calling
new_pool_data and remove a layer of indirection.
Signed-off-by: Michael Clark
---
include/tcg/tcg.h| 16 --
tcg/tcg.c
adata and x86-tablegen.py python script.
- includes x86 metadata opcode and operand documentation.
- addressed non-whitespace related checkpatch.pl warnings.
Michael Clark (4):
x86-disas: add x86-mini instruction set metadata
x86-disas: add x86-mini metadata documentation
x86-disas: add x86-
add detailed information on the instruction opcode encoding
format for LEX/VEX/EVEX prefix, map and opcode encoding, the
operand encoding format, the field order encoding format and
notes on instruction synthesis for parameterized opcodes.
Signed-off-by: Michael Clark
---
docs/x86-metadata.txt
that encodes operand field order
- x86 register enum and string table
- x86 opcode enum and string table
Signed-off-by: Michael Clark
---
scripts/x86-tablegen.py | 693
1 file changed, 693 insertions(+)
create mode 100755 scripts/x86-tablegen.py
diff
On 1/24/25 13:10, Michael Clark wrote:
+static x86_opc_prefix x86_table_make_prefix(const x86_opc_data *d,
+const x86_opr_data *o, const x86_ord_data *p)
+{
+x86_opc_prefix tp;
+memset(&tp, 0, sizeof(tp));
+
+/* extract prefix and synthesize width prefixes */
+sw
to save time on reviews. I had a look over the patch in light
of QEMU conventions I neglected due to it being portable code.
this is what I have found so far:
- use g_malloc/g_malloc0/g_free instead of malloc/calloc/free.
- remove duplicate unused definition of ctz/clz/popcnt.
- remove some magi
On 1/24/25 13:10, Michael Clark wrote:
this metadata is based on x86-csv with numerous inaccuracies
fixed plus conversion of legacy instructions to a new LEX format.
this metadata has been fuzz-tested against the LLVM disassembler
for x86-64 with 64-bit ISA coverage in the order of ~99.9
adata and x86-tablegen.py python script.
- includes x86 metadata opcode and operand documentation.
- addressed non-whitespace related checkpatch.pl warnings.
Michael Clark (4):
x86-disas: add x86-mini instruction set metadata
x86-disas: add x86-mini metadata documentation
x86-disas: add x86-
add detailed information on the instruction opcode encoding
format for LEX/VEX/EVEX prefix, map and opcode encoding, the
operand encoding format, the field order encoding format and
notes on instruction synthesis for parameterized opcodes.
Signed-off-by: Michael Clark
---
docs/x86-metadata.txt
that encodes operand field order
- x86 register enum and string table
- x86 opcode enum and string table
Signed-off-by: Michael Clark
---
scripts/x86-tablegen.py | 693
1 file changed, 693 insertions(+)
create mode 100755 scripts/x86-tablegen.py
diff
On 1/11/25 05:05, Paolo Bonzini wrote:
Il ven 10 gen 2025, 14:03 Michael Clark ha scritto:
On 1/11/25 00:07, Paolo Bonzini wrote:
Il ven 10 gen 2025, 10:52 Michael Clark ha
scritto:
a note to announce a port of the x86-mini disassembler to QEMU.
-https://github.com/michaeljclark/qemu/tree
On 1/11/25 05:05, Paolo Bonzini wrote:
Il ven 10 gen 2025, 14:03 Michael Clark ha scritto:
On 1/11/25 00:07, Paolo Bonzini wrote:
Il ven 10 gen 2025, 10:52 Michael Clark ha
scritto:
a note to announce a port of the x86-mini disassembler to QEMU.
- https://github.com/michaeljclark/qemu
On 1/11/25 00:07, Paolo Bonzini wrote:
Il ven 10 gen 2025, 10:52 Michael Clark ha scritto:
a note to announce a port of the x86-mini disassembler to QEMU.
- https://github.com/michaeljclark/qemu/tree/x86-mini
I assume the huge .h files are autogenerated? If so, QEMU cannot use them
without
self-contained and my stress and mental health is now under control.
also I have not yet run checkpatch.pl on this code. it is a preview.
x86-mini submaintainer.
Michael Clark.
--
ck at):
- https://www.metaparadigm.com/
You can pull my changes from my personal repo here:
- https://github.com/michaeljclark/riscv-qemu/tree/qemu-mjc
Apologies for the noise! and sorry for bringing GLib into
this dispute between me and Palmer. 🙃
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-b
On Wed, Nov 14, 2018 at 12:52 PM Palmer Dabbelt wrote:
> The following changes since commit
> cb968d275c145467c8b385a3618a207ec111eab1:
>
> Update version for v3.1.0-rc1 release (2018-11-13 18:16:14 +)
>
> are available in the Git repository at:
>
> git://github.com/riscv/riscv-qemu.git t
s I wrote, however perhaps thats just a matter
style with respect to writing (or re-writing) history.
Reviewed-by: Michael Clark
---
> target/riscv/translate.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f
for you to fetch changes up to 7c28f4da20e5585dce7d575691dac5392b7c6f78:
> >>
> >>RISC-V: Don't add NULL bootargs to device-tree (2018-10-17 13:02:30
> -0700)
> >>
> >> --------
> >
Hi All,
On Thu, Oct 11, 2018 at 7:22 AM Palmer Dabbelt wrote:
> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote:
> > On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
> >> we should really
> >> get the ball rolling on our big patch backlog.
> >
> > Yes, please do. Soft
On Mon, Sep 3, 2018 at 8:16 PM, Pranith Kumar wrote:
> On Mon, Sep 3, 2018 at 1:07 AM Michael Clark wrote:
> >
> > Thanks. I was just about to log an issue in the riscv-qemu issue tracker
> on GitHub.
> >
> > I reproduced it on my side. The fact that it is
Thanks. I was just about to log an issue in the riscv-qemu issue tracker on
GitHub.
I reproduced it on my side. The fact that it is causes QEMU user to crash
in translate.c is interesting.
I ran your program with -d in_asm and it appears to crash in thread::join
On Mon, Sep 3, 2018 at 7:58 PM, P
On Thu, Aug 2, 2018 at 3:57 PM, Philippe Mathieu-Daudé
wrote:
> Oops I just realized I forgot to Cc the QEMU list, doing it now.
>
> On 07/31/2018 07:40 AM, Edgar E. Iglesias wrote:
> > On Mon, Jul 30, 2018 at 03:22:46PM -0300, Philippe Mathieu-Daudé wrote:
> >> Hi, I'm getting this error while b
On Mon, 30 Jul 2018 at 10:46 PM, Peter Maydell
wrote:
> On 25 May 2018 at 14:17, Richard Henderson wrote:
> > On 05/24/2018 11:24 PM, Michael Clark wrote:
> >> This patch enables mhpmcounter3h through mhpmcounter31h on RV32.
> >> Previously the RV32 h versions (high
On Sat, Jul 28, 2018 at 11:49 AM, Alistair Francis wrote:
> Allow QEMU to be built to run on a RISC-V host.
>
> QEMU does not yet have a RISC-V TCG or user mode target port, but
> running other architectures on RISC-V using TCI does work.
>
There is this RISC-V TCG backend here:
https://github.
On Fri, May 18, 2018 at 8:02 PM, Igor Mammedov wrote:
> On Fri, 18 May 2018 14:10:24 +1200
> Michael Clark wrote:
>
> > On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov
> wrote:
> >
> > > cpu_init() was removed since 2.12, so drop the define that is now
> unu
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_u.c | 15 +++
> 1 fi
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/spike.c | 10 --
> 1 file cha
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/riscv_hart.c | 7 +++
> 1 file cha
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/virt.c | 5 ++---
> 1 file cha
On Wed, Jul 18, 2018 at 8:27 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_e.c | 12 ++--
> 1 fi
On Tue, 10 Jul 2018 at 12:29 PM, Alistair Francis
wrote:
> Add build time support for the VirtIO block device. This allows us to
> attach a drive using the virtio-blk-device.
I’m not sure what has changed in master, but VirtIO block and net for both
softmmu-riscv32 and softmmu-riscv64 were prev
On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis
wrote:
> On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote:
> > What is the state of the sifive_u emulation? When I tried to boot a bbl
> > with an included kernel I get these errors:
> >
> > qemu-system-riscv64: plic: invalid register write:
> On 23/06/2018, at 1:07 PM, Peter Maydell wrote:
>
> On 22 June 2018 at 20:30, Alistair Francis wrote:
>> Connect the Xilinx PCIe device based on the device tree included in the
>> HiFive Unleashed ROM.
>
> Did you consider using the 'gpex' generic PCIe controller here?
Yes. Alastair and I
; Signed-off-by: Philippe Mathieu-Daudé
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/virt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index ad03113e0f..34d48993a2 100644
> --- a/hw/riscv/virt.c
&g
On Fri, May 25, 2018 at 7:53 PM, Laurent Vivier wrote:
> Le 25/05/2018 à 09:22, Michael Clark a écrit :
> > Refer to the RISC-V PSABI specification for details:
> >
> > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
> >
> > Cc: Michae
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Laurent Vivier
Cc: Richard Henderson
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 8
1 file changed, 8
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier wrote:
> Le 23/05/2018 à 02:15, Michael Clark a écrit :
> > Refer to the RISC-V PSABI specification for details:
> >
> > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
> >
> > Cc: Michae
This patch enables mhpmcounter3h through mhpmcounter31h on RV32.
Previously the RV32 h versions (high 32-bits of 64-bit counters)
of these counters would trap with an illegal instruction instead
of returning 0 as intended.
Reported-by: Richard Henderson
Signed-off-by: Michael Clark
---
target
On Fri, May 25, 2018 at 9:54 AM, Richard Henderson wrote:
> In the latest Coverity scan, it reports
>
> 405if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) {
> 406return 0;
> 407}
> 408#if defined(TARGET_RISCV32)
> 409if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_M
to the MMU.
Michael.
On Wed, May 23, 2018 at 12:14 PM, Michael Clark wrote:
> - Inline PTE_TABLE check for better readability
> - Change access checks from ternary operator to if
> - Improve readibility of User page U mode and SUM test
> - Disallow non U mode from fetching from User p
is
Signed-off-by: Michael Clark
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c | 172
hw/riscv/virt.c | 67 +++
include/hw/riscv/boot.h | 30 +
4 files changed, 213 insertions(+), 57 deletions(-)
crea
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c | 4 +++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 326b0f434cff..02721d43c474 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-authored-by: Kito Cheng
Co-authored-by: Michael Clark
Signed-off-by: Michael Clark
---
linux-user/riscv/cpu_loop.c | 14 +-
target/riscv/cpu.h | 4
target/riscv/cpu_user.h | 3 ++-
3 files changed, 19
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
disas/riscv.c | 138
o consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 2 +
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Emilio G. Cota
Signed-off-by: Michael Clark
Reviewed
From: Richard Henderson
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8
Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Reported-by: Vincent Siles
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 28e28d932f7c
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Laurent Vivier
Cc: Richard Henderson
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 8
1 file changed, 8
s and processors that don't
implement PMP will trap on accesses to pmp* CSRs.
PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
-
s are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-Authored-by: Johannes Haring
Signed-off-by: Mi
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e.c | 4 ++--
hw/riscv/sifive_u.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index e4ecb7aa4bb6..159209199537 100644
--- a/hw
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/csr.c | 56 +++---
1 file
-off-by: Michael Clark
---
target/riscv/translate.c | 158 +++
1 file changed, 158 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fd21b133a5a4..e488101ff56d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ad03113e0f72..321fa6e8122a 100644
--- a/hw/riscv/virt.c
+++ b/hw
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_helper.c | 18
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 18 ++
target/riscv/csr.c | 35
Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 8
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 22 +-
target/riscv/op_helper.c | 24 +++-
4 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/riscv
riscv_set_mode to riscv_cpu_set_mode
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
linux-user/riscv/signal.c | 4 ++--
target/riscv/cpu.h| 21 ++---
target/riscv/cpu_helper.c | 10 +-
target/riscv
tatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
Co-authored-by: Richard Henderson
Co-aut
the
count of pending interrupts is not used.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
hw/riscv/sifive_plic.c | 49 +++---
include/hw/riscv
r and
software interrupts by other interrupt controller models.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c| 13 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Matthew Suozzo
Signed-off-by: Michael Clark
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Cl
her paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bit
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3d4..e0608e6d5f08 100644
Francis
Signed-off-by: Michael Clark
---
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 18 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 857 +
target/riscv/gdbstub.c | 10 +-
target/riscv/op_helper.c | 611
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/helper.c | 34
PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 2 --
target/riscv/helper.c | 64
irt bbl/linux-4.16-rc2 board test: pass
* sifive_e board test (HiFive1 binaries): pass
* sifive_u board test (HiFive Unleashed): pass
* riscv-tests: pass
* checkpatch: pass
Kito Cheng (1):
RISC-V: linux-user support for RVE ABI
Michael Clark (27):
RISC-V: Update address bits to support sv39
to maintain reconfigurable hardware support in a SiFive tree. I'll
leave the RFC proper for another email. This is just an abstract.
BTW - there are plently of others you can get to accept this patch ;-) See
the 'Cc.
Signed-off-by: Antony Pavlov
> Cc: Michael Clark
> Cc: Palmer Da
On Fri, May 11, 2018 at 3:52 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> Cc: Michael Clark
> Cc: Palmer Dabbelt
> Cc: Sagar Karandikar
> Cc: Bastian Koppelmann
> Signed-off-by: Richard Henderson
>
I'm not against this change but it conflicts w
On Sun, May 13, 2018 at 12:52 PM, Philippe Mathieu-Daudé
wrote:
> On 05/11/2018 12:52 AM, Richard Henderson wrote:
> > Cc: Michael Clark
> > Cc: Palmer Dabbelt
> > Cc: Sagar Karandikar
> > Cc: Bastian Koppelmann
> > Signed-off-by: Richard Henderson
>
&
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis wrote:
> To allow Linux to ennumerate devices on the /soc/ node set it as a
> "simple-bus".
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_u.c | 2 +-
> 1 file c
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_e.c | 97 +++--
> include/hw/riscv/sifive_e.h | 16 +-
> 2 files changed, 86
On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov wrote:
> cpu_init() was removed since 2.12, so drop the define that is now unused.
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Philippe Mathieu-Daudé
>
Reviewed-by: Michael Clark
---
> v2:
> * refine commi
On Sat, May 12, 2018 at 12:43 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> This is now handled properly by the generic softfloat code.
>
> Cc: Michael Clark
> Cc: Palmer Dabbelt
> Cc: Sagar Karandikar
> Cc: Bastian Koppelmann
> Signed-off-by: Ric
g in the device tree. e.g. we allocate and resolve phandles
vs hardcoding them. We can alwauys make a follow up commits to move some of
these magic numbers into constants in the headers, preferably with enum vs
#define.
Reviewed-by: Michael Clark
---
> hw/riscv/sifive_u.c | 2 +-
> 1 file
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis wrote:
> Connect the Cadence GEM ethernet device. This also requires us to
> expose the plic interrupt lines.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> default-configs/riscv32-softmmu.
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_u.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u
me TYPE_RISCV_U54_SOC to TYPE_RISCV_U_SOC
- Rename SiFiveU54State SiFiveUSOC (I don't think we need the State suffix
for the SOC)
Assuming we can do the renames to keep the SiFive U Series machine/SOC
general:
Reviewed-by: Michael Clark
---
> hw/riscv/sifive_u.c | 90
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