[PATCH v3] target/riscv: pmp: Ignore writes when RW=01

cfg.MML is set. Signed-off-by: Mayuresh Chitale Reviewed-by: Alistair Francis --- Changes in v3: - Rebase on latest riscv-to-apply.next - Add reviewed-by Changes in v2: - Default RW to 00 in case of an illegal value target/riscv/pmp.c | 5 + 1 file changed, 5 insertions(+) di

[PATCH v2] target/riscv: pmp: Clear pmp/smepmp bits on reset

spec, also clear the 'A' field of pmp entries. Signed-off-by: Mayuresh Chitale --- Changes in v2: - Rebase on latest riscv-to-apply.next - Clear 'A' field. target/riscv/cpu.c | 11 +++ target/riscv/pmp.c | 10 ++ target/riscv/pmp.h | 2 ++ 3 files change

[PATCH v2] Add epmp to extensions list and rename it to smepmp

From: Himanshu Chauhan Smepmp is a ratified extension which qemu refers to as epmp. Rename epmp to smepmp and add it to extension list so that it is added to the isa string. Signed-off-by: Himanshu Chauhan Signed-off-by: Mayuresh Chitale Reviewed-by: Daniel Henrique Barboza --- Changes in v2

Re: [PATCH] target/riscv: pmp: Clear pmp/smepmp bits on reset

Hi Vladimir, On Fri, Oct 6, 2023 at 5:08 PM Vladimir Isaev wrote: > > Hi Mayuresh, > > 25.09.2023 14:09, Mayuresh Chitale wrote: > > As per the Priv and Smepmp specifications, certain bits such as the 'L' > > bit of pmp entries and mseccfg.MML can only b

Re: [PATCH v2] target/riscv: pmp: Ignore writes when RW=01

On Mon, Oct 9, 2023 at 6:56 AM Alistair Francis wrote: > > On Mon, Sep 25, 2023 at 9:11 PM Mayuresh Chitale > wrote: > > > > As per the Priv spec: "The R, W, and X fields form a collective WARL > > field for which the combinations with R=0 and W=1 are reserved.&qu

Re: [PATCH] Add epmp to extensions list and rename it to smepmp

On Wed, Oct 11, 2023 at 8:45 AM Alistair Francis wrote: > > On Mon, Sep 25, 2023 at 9:08 PM Mayuresh Chitale > wrote: > > > > From: Himanshu Chauhan > > > > Smepmp is a ratified extension which qemu refers to as epmp. > > Rename epmp to smepmp and add

[PATCH v2] target/riscv: pmp: Ignore writes when RW=01

cfg.MML is set. Signed-off-by: Mayuresh Chitale --- target/riscv/pmp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5b14eb511a..8e25f145e0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -120,6 +120,11 @@ static void pmp

[PATCH] target/riscv: pmp: Clear pmp/smepmp bits on reset

As per the Priv and Smepmp specifications, certain bits such as the 'L' bit of pmp entries and mseccfg.MML can only be cleared upon reset and it is necessary to do so to allow 'M' mode firmware to correctly reinitialize the pmp/smpemp state across reboots. Signed-off-

[PATCH] Add epmp to extensions list and rename it to smepmp

From: Himanshu Chauhan Smepmp is a ratified extension which qemu refers to as epmp. Rename epmp to smepmp and add it to extension list so that it is added to the isa string. Signed-off-by: Himanshu Chauhan Signed-off-by: Mayuresh Chitale Reviewed-by: Daniel Henrique Barboza --- target/riscv

Re: [PATCH] target/riscv: pmp: Ignore writes when RW=01

On Mon, Sep 18, 2023 at 7:02 AM Alistair Francis wrote: > > On Thu, Sep 14, 2023 at 10:35 PM Mayuresh Chitale > wrote: > > > > As per the Priv spec: "The R, W, and X fields form a collective WARL > > field for which the combinations with R=0 and W=1 are reser

Re: [PATCH] target/riscv: pmp: Clear pmp/smepmp bits on reset

On Tue, Sep 19, 2023 at 10:10 AM Alistair Francis wrote: > > On Thu, Sep 7, 2023 at 4:25 PM Mayuresh Chitale > wrote: > > > > As per the Priv and Smepmp specifications, certain bits such as the 'L' > > bit of pmp entries and mseccfg.MML can only be cleared

[PATCH] target/riscv: pmp: Ignore writes when RW=01

cfg.MML is set. Signed-off-by: Mayuresh Chitale --- target/riscv/pmp.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index f3eb6e6585..5b430be18c 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -119,6 +119,14 @@ static bool pmp

[PATCH] target/riscv: pmp: Clear pmp/smepmp bits on reset

As per the Priv and Smepmp specifications, certain bits such as the 'L' bit of pmp entries and mseccfg.MML can only be cleared upon reset and it is necessary to do so to allow 'M' mode firmware to correctly reinitialize the pmp/smpemp state across reboots. Signed-off-

[PATCH v5 0/3] Smstateen FCSR

description - Reuse TB_FLAGS.HS_FS for smstateen - Convert smstateen_fcsr_check to function - Add fcsr check for zdinx Mayuresh Chitale (3): target/riscv: smstateen check for fcsr target/riscv: Reuse tb->flags.FS target/riscv: smstateen knobs target/riscv/cpu.c |

[PATCH v5 3/3] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b

[PATCH v5 1/3] target/riscv: smstateen check for fcsr

Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec and check for it when accessing the fcsr register and its fields. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/riscv

[PATCH v5 2/3] target/riscv: Reuse tb->flags.FS

When misa.F is 0 tb->flags.FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li --- target/riscv/cpu_helpe

Re: [PATCH v4 1/3] target/riscv: smstateen check for fcsr

On Wed, May 17, 2023 at 8:42 AM Alistair Francis wrote: > > On Tue, May 2, 2023 at 12:00 AM Mayuresh Chitale > wrote: > > > > If smstateen is implemented and smtateen0.fcsr is clear and misa.F > > is off then the floating point operations must return illegal > >

[PATCH v4 0/3] Smstateen FCSR

smstateen_fcsr_check to function - Add fcsr check for zdinx Mayuresh Chitale (3): target/riscv: smstateen check for fcsr target/riscv: Reuse tb->flags.FS target/riscv: smstateen knobs target/riscv/cpu.c | 3 ++- target/riscv/cpu_helper.c | 6 ++ target/ri

[PATCH v4 3/3] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b

[PATCH v4 1/3] target/riscv: smstateen check for fcsr

If smstateen is implemented and smtateen0.fcsr is clear and misa.F is off then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c | 15 +++ 1

[PATCH v4 2/3] target/riscv: Reuse tb->flags.FS

When misa.F is 0 tb->flags.FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/cpu_helper.c | 6 ++ tar

[PATCH v3 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b

[PATCH v3 1/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and smtateen0.fcsr is clear and misa.F is off then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c | 15 +++ 1

[PATCH v3 2/4] target/riscv: Reuse tb->flags.FS

When misa.F is 0 tb->flags.FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu_helper.c | 9 + target/riscv/translate.c |

[PATCH v3 0/4] Smstateen FCSR

Mayuresh Chitale (4): target/riscv: smstateen check for fcsr target/riscv: Reuse tb->flags.FS target/riscv: check smstateen fcsr flag target/riscv: smstateen knobs target/riscv/cpu.c| 3 ++- target/riscv/cpu_helper.c | 9 +++ target/riscv/cs

[PATCH v3 3/4] target/riscv: check smstateen fcsr flag

If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvd.c.inc | 13 ++--- target/riscv/insn_trans/trans_rvf.c.inc | 24 ++--- target

Re: [RFC PATCH v2 3/4] target/riscv: check smstateen fcsr flag

On Sat, Apr 15, 2023 at 6:55 AM Weiwei Li wrote: > > > On 2023/4/15 00:02, Mayuresh Chitale wrote: > > If misa.F and smstateen_fcsr_ok flag are clear then all the floating > > point instructions must generate an appropriate exception. > > > > Signed-off-by: Mayur

Re: [RFC PATCH v2 2/4] target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS

On Sat, Apr 15, 2023 at 7:15 AM Weiwei Li wrote: > > > On 2023/4/15 00:02, Mayuresh Chitale wrote: > > When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can > > be used to save the current state of smstateen0.FCSR check which is > > needed by the floating

Re: [RFC PATCH v2 1/4] target/riscv: smstateen check for fcsr

On Sat, Apr 15, 2023 at 6:32 AM Weiwei Li wrote: > > > On 2023/4/15 00:01, Mayuresh Chitale wrote: > > If smstateen is implemented and smtateen0.fcsr is clear and misa.F > > is off then the floating point operations must return illegal > > instruction exception or v

[RFC PATCH v2 2/4] target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS

When misa.F is clear, TB_FLAGS.MSTATUS_HS_FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu_helper.c | 12 target/riscv/translate.c

[RFC PATCH v2 0/4] Smstateen FCSR

in v2: - Improve patch 1 description - Reuse TB_FLAGS.HS_FS for smstateen - Convert smstateen_fcsr_check to function - Add fcsr check for zdinx Mayuresh Chitale (4): target/riscv: smstateen check for fcsr target/riscv: Reuse TB_FLAGS.MSTATUS_HFS_FS target/riscv: check smstateen fcsr flag

[RFC PATCH v2 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b

[RFC PATCH v2 1/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and smtateen0.fcsr is clear and misa.F is off then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 23 +++ 1 file changed

[RFC PATCH v2 3/4] target/riscv: check smstateen fcsr flag

If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvd.c.inc | 13 target/riscv/insn_trans/trans_rvf.c.inc | 24

Re: [RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags

On Tue, Apr 11, 2023 at 7:17 AM Richard Henderson wrote: > > On 4/10/23 07:13, Mayuresh Chitale wrote: > > The state of smstateen0.FCSR bit impacts the execution of floating point > > instructions when misa.F==0. Add a field in the tb->flags which stores > > the curre

Re: [RFC PATCH 3/4] target/riscv: check smstateen fcsr flag

On Tue, Apr 11, 2023 at 7:23 AM Richard Henderson wrote: > > On 4/10/23 07:13, Mayuresh Chitale wrote: > > +#ifndef CONFIG_USER_ONLY > > +#define smstateen_fcsr_check(ctx) do { \ > > +if (!ctx->smstateen_fcsr_ok) { \ > > +if (ctx->virt_enabled) { \

Re: [RFC PATCH 3/4] target/riscv: check smstateen fcsr flag

On Mon, Apr 10, 2023 at 8:00 PM liweiwei wrote: > > > On 2023/4/10 22:13, Mayuresh Chitale wrote: > > If misa.F and smstateen_fcsr_ok flag are clear then all the floating > > point instructions must generate an appropriate exception. > > > > Signed-off-by: Mayur

Re: [RFC PATCH 1/4] target/riscv: smstateen check for fcsr

On Mon, Apr 10, 2023 at 8:14 PM liweiwei wrote: > > > On 2023/4/10 22:13, Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the > > floating point operations must return illegal instruction exception > > or virtual instruction

[RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags

The state of smstateen0.FCSR bit impacts the execution of floating point instructions when misa.F==0. Add a field in the tb->flags which stores the current state of smstateen0.fcsr and will be used by floating point translation routines. Signed-off-by: Mayuresh Chitale --- target/riscv/cp

[RFC PATCH 0/4] Smstateen FCSR implementation

. Mayuresh Chitale (4): target/riscv: smstateen check for fcsr target/riscv: Add fcsr field in tb->flags target/riscv: check smstateen fcsr flag target/riscv: smstateen knobs target/riscv/cpu.c| 3 ++- target/riscv/cpu.h| 4 target/ri

[RFC PATCH 1/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 3 +++ target/riscv/csr.c | 25 - 2

[RFC PATCH 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b

[RFC PATCH 3/4] target/riscv: check smstateen fcsr flag

If misa.F and smstateen_fcsr_ok flag are clear then all the floating point instructions must generate an appropriate exception. Signed-off-by: Mayuresh Chitale --- target/riscv/insn_trans/trans_rvf.c.inc | 24 --- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 2

Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr

On Fri, Mar 24, 2023 at 7:01 PM liweiwei wrote: > > > On 2022/11/21 07:35, Alistair Francis wrote: > > On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale > > wrote: > >> If smstateen is implemented and sstateen0.fcsr is clear then the floating > >> po

[PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state

cpu_by_arch_id which performs lookup based on the sparse physical hart IDs. Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- hw/intc/riscv_aclint.c | 16 hw/intc/riscv_aplic.c | 4 ++-- hw/intc/riscv_imsic.c | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions

[PATCH 0/2] Risc-V CPU state by hart ID

sparse instead of the contigous logical CPU id. Mayuresh Chitale (2): target/riscv: cpu: Implement get_arch_id callback hw: intc: Use cpu_by_arch_id to fetch CPU state hw/intc/riscv_aclint.c | 16 hw/intc/riscv_aplic.c | 4 ++-- hw/intc/riscv_imsic.c | 6 +++--- target/riscv

[PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback

Implement the callback for getting the architecture-dependent CPU ID ie mhartid. Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dd2f0c753..467d8467a3

[PATCH v3 2/3] target/riscv: Extend isa_ext_data for single letter extensions

extensions from the list of single letter extensions as those are not supported yet. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 41 +++-- 1 file changed, 23 inserti

[PATCH v3 3/3] target/riscv: kvm: Support selecting VCPU extensions

Set the state of each ISA extension on the vcpu depending on what is set in the CPU property and what is allowed by KVM for that extension. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 - target/riscv/kvm.c

[PATCH v3 1/3] update-linux-headers: Version 6.1-rc8

Sync headers with kernel commit 76dcd734eca2 Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- include/standard-headers/drm/drm_fourcc.h | 34 - include/standard-headers/linux/ethtool.h | 63 +++- include/standard-headers/linux/fuse.h | 6 +- .../linux

[PATCH v3 0/3] target/riscv: Apply KVM policy to ISA extensions

https://github.com/mdchitale/qemu.git Changes in v3: - Address comments from Bin Meng Changes in v2: - Rebase to latest riscv-to-apply.next - Update linux headers to version 6.1-rc8 - Add reviewed by tags Mayuresh Chitale (3): update-linux-headers: Version 6.1-rc8 target/riscv: Extend isa_ext_dat

[PATCH v2 1/3] update-linux-headers: Version 6.1-rc8

Sync headers with kernel commit 76dcd734eca2 Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- include/standard-headers/drm/drm_fourcc.h | 34 - include/standard-headers/linux/ethtool.h | 63 +++- include/standard-headers/linux/fuse.h | 6 +- .../linux

[PATCH v2 2/3] target/riscv: Extend isa_ext_data for single letter extensions

extensions from the list of single letter extensions as those are not supported yet. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 41 +++-- 1 file changed, 23 insertions(+), 18 deletions(-)

[PATCH v2 0/3] target/riscv: Apply KVM policy to ISA extensions

https://github.com/mdchitale/qemu.git Changes in v2: - Rebase to latest riscv-to-apply.next - Update linux headers to version 6.1-rc8 - Add reviewed by tags Mayuresh Chitale (3): update-linux-headers: Version 6.1-rc8 target/riscv: Extend isa_ext_data for single letter extensions target/riscv

[PATCH v2 3/3] target/riscv: kvm: Support selecting VCPU extensions

Set the state of each ISA extension on the vcpu depending on what is set in the CPU property and what is allowed by KVM for that extension. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 - target/riscv/kvm.c

[PATCH v1 1/3] update-linux-headers: Version 6.1-rc2

Sync headers with kernel commit 247f34f7b803 Signed-off-by: Mayuresh Chitale --- include/standard-headers/drm/drm_fourcc.h | 34 - include/standard-headers/linux/ethtool.h | 63 +++- include/standard-headers/linux/fuse.h | 6 +- .../linux/input-event-codes.h

[PATCH v1 0/3] target/riscv: Apply KVM policy to ISA extensions

Currently the single and multi letter ISA extensions exposed to the guest vcpu don't confirm to the KVM policies. This patchset updates the kvm headers and applies policies set in KVM to the extensions exposed to the guest. Mayuresh Chitale (3): update-linux-headers: Version 6.1-rc2 t

[PATCH v1 2/3] target/riscv: Extend isa_ext_data for single letter extensions

extensions from the list of single letter extensions as those are not supported yet. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 41 +++-- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cp

[PATCH v1 3/3] target/riscv: kvm: Support selecting VCPU extensions

Set the state of each ISA extension on the vcpu depending on what is set in the CPU property and what is allowed by KVM for that extension. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 11 - target/riscv/kvm.c | 88 ++-- target

[PATCH v11 5/5] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v11 4/5] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/csr.c| 23

[PATCH v11 3/5] target/riscv: generate virtual instruction exception

This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion

[PATCH v11 2/5] target/riscv: smstateen check for h/s/envcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/csr.c | 87

[PATCH v11 0/5] RISC-V Smstateen support

- Fix *stateen0h index calculation Changes in v2: - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. Mayuresh Chitale (5): target/riscv: Add smstateen support target/riscv: smstateen check for h/s/envcfg target/riscv: generate virtual instruction exception target/riscv

[PATCH v11 1/5] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target

[PATCH v10 4/5] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23 target/riscv/insn_trans

[PATCH v10 5/5] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v10 2/5] target/riscv: smstateen check for h/s/envcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/csr.c | 87

[PATCH v10 1/5] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target

[PATCH v10 0/5] RISC-V Smstateen support

isa_edata_arr as described in rule #3 the comment. Changes in v4: - Fix build issue with riscv32/riscv64-linux-user targets Changes in v3: - Fix coding style issues - Fix *stateen0h index calculation Changes in v2: - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. Mayuresh

[PATCH v10 3/5] target/riscv: generate virtual instruction exception

This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 9 - 1 file changed, 8 insertions(+), 1 deletion

[PATCH v9 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aee14a239a..1252ca71b3

[PATCH v9 3/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23 + target/riscv

[PATCH v9 0/4] RISC-V Smstateen support

in m/h/stateen registers as writeable by default. Mayuresh Chitale (4): target/riscv: Add smstateen support target/riscv: smstateen check for h/s/envcfg target/riscv: smstateen check for fcsr target/riscv: smstateen knobs target/riscv/cpu.c| 2 + target/riscv

[PATCH v9 1/4] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 4

[PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/csr.c | 87

[PATCH v8 3/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23 + target/riscv

[PATCH v8 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..d8a0f4e700 100644 --- a/target

[PATCH v8 2/4] target/riscv: smstateen check for h/s/envcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 87 ++ 1 file changed

[PATCH v8 1/4] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 4

[PATCH v8 0/4] RISC-V Smstateen support

rule #3 the comment. Changes in v4: - Fix build issue with riscv32/riscv64-linux-user targets Changes in v3: - Fix coding style issues - Fix *stateen0h index calculation Changes in v2: - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. Mayuresh Chitale (4): target/riscv

Re: [PATCH v7 3/4] target/riscv: smstateen check for fcsr

On Wed, 2022-08-03 at 16:32 +0800, Weiwei Li wrote: > 在 2022/8/2 上午1:18, Mayuresh Chitale 写道: > > If smstateen is implemented and sstateen0.fcsr is clear then the > > floating point operations must return illegal instruction > > exception. > > I think this is not corre

Re: [PATCH v7 2/4] target/riscv: smstateen check for h/senvcfg

On Wed, 2022-08-03 at 16:24 +0800, Weiwei Li wrote: > 在 2022/8/2 上午1:18, Mayuresh Chitale 写道: > > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if > > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an > > illegal instruction trap is generated. &

Re: [PATCH v7 1/4] target/riscv: Add smstateen support

On Wed, 2022-08-03 at 16:15 +0800, Weiwei Li wrote: > 在 2022/8/2 上午1:18, Mayuresh Chitale 写道: > > Smstateen extension specifies a mechanism to close > > the potential covert channels that could cause security issues. > > > > This patch adds the CSRs defined in th

[PATCH v7 1/4] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 4

[PATCH v7 3/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23 + target/riscv/insn_trans/trans_rvf.c.inc | 40

[PATCH v7 0/4] RISC-V Smstateen support

Changes in v2: - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. Anup Patel (1): target/riscv: Force disable extensions if priv spec version does not match Mayuresh Chitale (4): target/riscv: Add smstateen support target/riscv: smstateen check for h/senvcfg target

[PATCH v7 4/4] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..d8a0f4e700 100644 --- a/target

[PATCH v7 2/4] target/riscv: smstateen check for h/senvcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- roms/opensbi | 2 +- target/riscv/csr.c | 83

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

On Thu, 2022-07-28 at 09:09 +0100, Ben Dooks wrote: > On 28/07/2022 07:15, Mayuresh Chitale wrote: > > On Mon, 2022-07-25 at 15:23 +0800, Weiwei Li wrote: > > > 在 2022/7/24 下午11:49, Mayuresh Chitale 写道: > > > > On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote:

Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

On Fri, 2022-07-22 at 08:45 +0800, Weiwei Li wrote: > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > Accesses to henvcfg, henvcfgh and senvcfg are allowed only if > > corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an > > illegal instruction trap is generated. &

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

On Mon, 2022-07-25 at 15:23 +0800, Weiwei Li wrote: > > 在 2022/7/24 下午11:49, Mayuresh Chitale 写道: > > On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote: > > > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > > > If smstateen is implemented and sstatee

Re: [PATCH v6 1/5] target/riscv: Add smstateen support

On Mon, 2022-07-25 at 15:11 +0800, Weiwei Li wrote: > 在 2022/7/24 下午11:39, Mayuresh Chitale 写道: > > On Fri, 2022-07-22 at 08:31 +0800, Weiwei Li wrote: > > > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > > > Smstateen extension specifies a mechanism to close > &g

Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr

On Fri, 2022-07-22 at 09:42 +0800, Weiwei Li wrote: > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > If smstateen is implemented and sstateen0.fcsr is clear then the > > floating point operations must return illegal instruction > > exception. > > > >

Re: [PATCH v6 1/5] target/riscv: Add smstateen support

On Fri, 2022-07-22 at 08:31 +0800, Weiwei Li wrote: > 在 2022/7/21 下午11:31, Mayuresh Chitale 写道: > > Smstateen extension specifies a mechanism to close > > the potential covert channels that could cause security issues. > > > > This patch adds the CSRs defined in th

[PATCH v6 5/5] target/riscv: smstateen knobs

Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db2b8e4d30..2b7ed95396 100644 --- a/target

[PATCH v6 4/5] target/riscv: smstateen check for AIA/IMSIC

If smstateen is implemented then accesses to AIA registers CSRS, IMSIC CSRs and other IMSIC registers is controlled by setting of corresponding bits in mstateen/hstateen registers. Otherwise an illegal instruction trap or virtual instruction trap is generated. Signed-off-by: Mayuresh Chitale

[PATCH v6 3/5] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c| 23 ++ target/riscv/insn_trans/trans_rvf.c.inc | 38

[PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 100 + 1 file changed, 93

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