[Qemu-devel] Telling qemu to run for a number of guest milliseconds and then pause

2018-08-28 Thread Martin Schroeder via Qemu-devel
I'm working on an interface between qemu and an in house testing suite and one of the things I would like to do is tell qemu to run the guest for a number of guest milliseconds and then pause execution of the guest. I do not want qemu to raise a debug exception. I just want it to pause (ie sleep o

Re: [Qemu-devel] Modeling a device controlled by combination of GPIO and UART

2018-08-22 Thread Martin Schroeder via Qemu-devel
gpio pin. I need to make sure that it gets called every time master device calls qemu_set_irq. What's the mechanism behind this behavior and how can I deliver gpio change to the slave? On Tue, Aug 21, 2018 at 3:57 PM Peter Maydell wrote: > > On 21 August 2018 at 14:29, Martin Schroeder via

[Qemu-devel] Modeling a device controlled by combination of GPIO and UART

2018-08-21 Thread Martin Schroeder via Qemu-devel
I'd like to add a virtual device that is controlled by a couple of GPIO pins on my controller (cortex-m4) and a serial port. I suppose I can derive it from SSISlaveClass to make the new device a serial slave. But how do I connect GPIOs? I want the slave device to be notified when guest firmware t

Re: [Qemu-devel] Simulating a composite machine

2018-08-20 Thread Martin Schroeder via Qemu-devel
Is it that I need to add emulation for CP10 and CP11? On Mon, Aug 20, 2018 at 8:29 PM Martin Schroeder wrote: > > Sent it off as reply instead of reply all.. my bad. > > I was also surprised that it was mid into an instruction. The code > works fine on STM32 but if FPU is not enabled on the STM32

Re: [Qemu-devel] Simulating a composite machine

2018-08-20 Thread Martin Schroeder via Qemu-devel
Sent it off as reply instead of reply all.. my bad. I was also surprised that it was mid into an instruction. The code works fine on STM32 but if FPU is not enabled on the STM32 then I believe the code will fault in much the same way. I have had this problem before and it was also hard faulting in

[Qemu-devel] Simulating a composite machine

2018-08-19 Thread Martin Schroeder via Qemu-devel
Is it possible to instantiate multiple CPUs of different architectures and simuate them with different images at the same time? Some examples include ARM socs with m3/m4 coprocessor core but also boards with multiple processors where it is desirable to connect the chips over for example virtual SPI