On Thu, 17 Jul 2025 16:45:37 +0100,
Mark Burton wrote:
>
> So long as we can also switch to the emulated GIC when we want/need
> to :-) (looking at you KVM :-))
KVM really doesn't need such a non-feature. Specially as it cannot be
implemented without an actual GICv3 in HW, for obvious reasons.
On Tue, 15 Jul 2025 12:15:52 +0100,
Alex Bennée wrote:
> - do we know which Apple silicon supports FEAT_NV2?
M2 and latter definitely support FEAT_NV2. That's how KVM NV support
has been developed for two years until I was given better HW.
Whether Apple supports NV on M2 in HVF, I have no ide
On Mon, 07 Jul 2025 15:46:04 +0100,
Peter Maydell wrote:
>
> On Mon, 7 Jul 2025 at 15:32, Marc Zyngier wrote:
> >
> > On Mon, 07 Jul 2025 10:53:38 +0100,
> > Peter Maydell wrote:
> > >
> > > On Mon, 7 Jul 2025 at 10:30, Eric Auger wrote:
> > &g
On Mon, 07 Jul 2025 10:53:38 +0100,
Peter Maydell wrote:
>
> On Mon, 7 Jul 2025 at 10:30, Eric Auger wrote:
> >
> > Hi Peter, Marc,
> >
> > On 7/4/25 2:22 PM, Peter Maydell wrote:
> > > I suppose the system registers probably generally Just Work
> > > via the sysreg GET/SET_ONE_REG API, but won'
On Fri, 04 Jul 2025 13:01:05 +0100,
Peter Maydell wrote:
>
> On Wed, 2 Jul 2025 at 17:31, Eric Auger wrote:
> >
> > From: Haibo Xu
> >
> > Allow virt arm machine to set the interrupt ID for the KVM
> > GIC maintenance interrupt.
> >
> > This setting must be done before the KVM_DEV_ARM_VGIC_CTRL
On Wed, 28 May 2025 00:52:40 +0100,
Miguel Luis wrote:
>
>
>
> > On 27 May 2025, at 16:52, Marc Zyngier wrote:
> >
> > On Tue, 27 May 2025 16:55:32 +0100,
> > Miguel Luis wrote:
> >>
>> Result on the guest: Splat at early_kvm_mode_cfg,
On Tue, 27 May 2025 16:55:32 +0100,
Miguel Luis wrote:
>
> Hi Marc,
>
> > On 27 May 2025, at 13:46, Marc Zyngier wrote:
> >
> > On Tue, 27 May 2025 14:24:31 +0100,
> > Miguel Luis wrote:
> >>
> >>
> >>
> >>> On 27 M
On Tue, 27 May 2025 14:11:41 +0100,
Eric Auger wrote:
>
> Hi Miguel, Marc,
>
> On 5/27/25 2:54 PM, Miguel Luis wrote:
> >
> >> On 27 May 2025, at 12:01, Marc Zyngier wrote:
> >>
> >> On Tue, 27 May 2025 12:33:23 +0100,
> >> Miguel Luis wr
On Tue, 27 May 2025 14:24:31 +0100,
Miguel Luis wrote:
>
>
>
> > On 27 May 2025, at 12:02, Marc Zyngier wrote:
> >
> > On Tue, 27 May 2025 12:40:35 +0100,
> > Miguel Luis wrote:
> >>
> >> Hi Marc,
> >>
> >>
On Tue, 27 May 2025 12:40:35 +0100,
Miguel Luis wrote:
>
> Hi Marc,
>
> > On 27 May 2025, at 07:39, Marc Zyngier wrote:
> >
> > Hi Eric,
> >
> > On Tue, 27 May 2025 07:24:32 +0100,
> > Eric Auger wrote:
> >>
> >> Now tha
On Tue, 27 May 2025 12:33:23 +0100,
Miguel Luis wrote:
>
> Hi Eric,
>
> > On 27 May 2025, at 06:24, Eric Auger wrote:
> >
> > Now that ARM nested virt has landed in kvm/next, let's turn the series
> > into a PATCH series. The linux header update was made against kvm/next.
> >
> > For gaining
Hi Eric,
On Tue, 27 May 2025 07:24:32 +0100,
Eric Auger wrote:
>
> Now that ARM nested virt has landed in kvm/next, let's turn the series
> into a PATCH series. The linux header update was made against kvm/next.
>
> For gaining virt functionality in KVM accelerated L1, The host needs to
> be bo
On Tue, 11 Mar 2025 16:28:10 +,
Cornelia Huck wrote:
>
> - I'm open to changing the source of the definitions from the sysregs
> file to the JSON definitions published by Arm; however, I first wanted
> to get the code using it right -- we can switch out the code generating
> the
On Fri, 07 Feb 2025 11:02:47 +,
Cornelia Huck wrote:
>
> From: Eric Auger
>
> Introduce scripts that automate the generation of system register
> definitions from a given linux source tree arch/arm64/tools/sysreg.
>
> Invocation of
> ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TR
The host CPU
> will choose the cryptographic algorithm.
>
> - For TCG, however, along with `pauth`, a couple of properties can be
> controlled -- they're are related to cryptographic algorithm choice.
>
> Thanks to Peter Maydell and Marc Zyngier for explaining m
On Fri, 20 Dec 2024 11:52:51 +,
Kashyap Chamarthy wrote:
>
> On Thu, Dec 19, 2024 at 03:41:56PM +, Marc Zyngier wrote:
> > On Thu, 19 Dec 2024 15:07:25 +,
> > Kashyap Chamarthy wrote:
> > >
> > > On Thu, Dec 19, 2024 at 12:26:29PM +, Marc Z
On Thu, 19 Dec 2024 17:51:44 +,
Daniel "P. Berrangé" wrote:
>
> On Thu, Dec 19, 2024 at 03:41:56PM +0000, Marc Zyngier wrote:
> > On Thu, 19 Dec 2024 15:07:25 +,
> > Kashyap Chamarthy wrote:
> > >
> > > On Thu, Dec 19, 2024 at 12:26:29PM
On Thu, 19 Dec 2024 15:07:25 +,
Kashyap Chamarthy wrote:
>
> On Thu, Dec 19, 2024 at 12:26:29PM +, Marc Zyngier wrote:
> > On Thu, 19 Dec 2024 11:35:16 +,
> > Kashyap Chamarthy wrote:
>
> [...]
>
> > > Consider this:
> > >
> > &g
On Thu, 19 Dec 2024 11:35:16 +,
Kashyap Chamarthy wrote:
>
> On Thu, Dec 12, 2024 at 11:04:30AM +0100, Eric Auger wrote:
>
> Hi Eric,
>
> > On 12/12/24 10:36, Cornelia Huck wrote:
> > > On Thu, Dec 12 2024, Daniel P. Berrangé wrote:
>
> [...]
>
> > >> Consider you mgmt app wants to set a
On Thu, 19 Dec 2024 12:38:50 +,
Daniel "P. Berrangé" wrote:
>
> On Thu, Dec 19, 2024 at 12:26:29PM +0000, Marc Zyngier wrote:
> > On Thu, 19 Dec 2024 11:35:16 +,
> > Kashyap Chamarthy wrote:
> > >
> > > On Thu, Dec 12, 2024 at 11:04:30AM
On Fri, 06 Dec 2024 11:21:53 +,
Cornelia Huck wrote:
>
> A respin/update on the aarch64 KVM cpu models. Also available at
> gitlab.com/cohuck/qemu arm-cpu-model-rfcv2
>
> Find Eric's original cover letter below, so that I do not need to
> repeat myself on the aspects that have not changed si
On Thu, 14 Nov 2024 09:03:24 +,
Zhou Wang wrote:
>
> Hi,
>
> I am tring to heterogeneous live migration on ARM64 host. Now I just use
> below kernel/qemu branch to have a try:
> https://github.com/hisilicon/kernel-dev/tree/private-v6.11-rc2-hisi-migrn-wip
> https://github.com/hisilicon/qemu/
On Fri, 25 Oct 2024 11:17:33 +0100,
Eric Auger wrote:
>
> Introduce scripts that automate the generation of system register
> definitions from a given linux source tree arch/arm64/tools/sysreg.
>
> Invocation of
> ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
> in scripts directory
On 2024-02-09 18:57, Peter Maydell wrote:
On Fri, 9 Feb 2024 at 16:00, Eric Auger wrote:
This series adds ARM Nested Virtualization support in KVM mode.
This is a respin of previous contributions from Miguel [1] and Haibo
[2].
This was tested with Marc's v11 [3] on Ampere HW with fedora L1
On Thu, 11 Jan 2024 09:39:18 +,
Philippe Mathieu-Daudé wrote:
>
> On 10/1/24 20:53, Philippe Mathieu-Daudé wrote:
> > The "aarch64" property is added to ARMCPU when the
> > ARM_FEATURE_AARCH64 feature is available. Rather than
> > checking whether the QOM property is present, directly
> > che
On Thu, 13 Jul 2023 13:35:57 +0100,
Kunkun Jiang wrote:
>
> For ARM, it will first send a DISCARD command to ITS and then
> establish the interrupt reporting channel for GICv3. The DISCARD
> will remove the pending interrupt. Interrupts that come before
> channel re-establishment are silently dis
On Mon, 06 Mar 2023 14:02:33 +,
Peter Maydell wrote:
>
> On Mon, 27 Feb 2023 at 16:37, Miguel Luis wrote:
> >
> > From: Haibo Xu
> >
> > Use the VGIC maintenance IRQ if VHE is requested. As per the ARM GIC
> > Architecture Specification for GICv3 and GICv4 Arm strongly recommends that
> > m
On Wed, 30 Nov 2022 02:52:35 +,
"chenxiang (M)" wrote:
>
> Hi,
>
> We boot the VM using following commands (with nvdimm on) (qemu
> version 6.1.50, kernel 6.0-r4):
How relevant is the presence of the nvdimm? Do you observe the failure
without this?
>
> qemu-system-aarch64 -machine
> virt
On Sat, 26 Nov 2022 06:33:15 +,
"chenxiang (M)" wrote:
>
>
> 在 2022/11/23 20:08, Marc Zyngier 写道:
> > On Wed, 23 Nov 2022 01:42:36 +,
> > chenxiang wrote:
> >> From: Xiang Chen
> >>
> >> Currently the number of MSI vectors co
On Wed, 23 Nov 2022 19:55:14 +,
Alex Williamson wrote:
>
> On Wed, 23 Nov 2022 12:08:05 +0000
> Marc Zyngier wrote:
>
> > On Wed, 23 Nov 2022 01:42:36 +,
> > chenxiang wrote:
> > >
> > > +static int vfio_pci_verify_msi_entry(struct vfio_pci
On Wed, 23 Nov 2022 01:42:36 +,
chenxiang wrote:
>
> From: Xiang Chen
>
> Currently the number of MSI vectors comes from register PCI_MSI_FLAGS
> which should be power-of-2 in qemu, in some scenaries it is not the same as
> the number that driver requires in guest, for example, a PCI driver
On Wed, 09 Nov 2022 06:21:18 +,
"chenxiang (M)" wrote:
>
> Hi Marc,
>
>
> 在 2022/11/8 20:47, Marc Zyngier 写道:
> > On Tue, 08 Nov 2022 08:08:57 +,
> > chenxiang wrote:
> >> From: Xiang Chen
> >>
> >> Currently the nu
On Tue, 08 Nov 2022 08:08:57 +,
chenxiang wrote:
>
> From: Xiang Chen
>
> Currently the numbers of MSI vectors come from register PCI_MSI_FLAGS
> which should be power-of-2, but in some scenaries it is not the same as
> the number that driver requires in guest, for example, a PCI driver wan
0067.html
> > v3: https://lists.nongnu.org/archive/html/qemu-arm/2022-09/msg00258.html
> > v2: https://lore.kernel.org/all/20220815062958.100366-1-gs...@redhat.com/T/
> > v1: https://lists.nongnu.org/archive/html/qemu-arm/2022-08/msg00013.html
> >
>
> Could you help
On Thu, 20 Oct 2022 00:57:32 +0100,
Gavin Shan wrote:
>
> For Marc's suggestion to add properties so that these high memory
> regions can be disabled by users. I can add one patch after this one
> to introduce the following 3 properties. Could you please confirm
> the property names are good enou
On Tue, 04 Oct 2022 01:26:27 +0100,
Gavin Shan wrote:
>
> After the improvement to high memory region address assignment is
> applied, the memory layout can be changed, introducing possible
> migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
> is disabled or enabled when the opti
> v3: really correctly check errno. This time for sure!
> ---
> target/arm/kvm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
sing the max of the two page sizes.
> >
> > Reported-by: Marc Zyngier
This is no longer a thing (and hasn't been for over 3 years! ;-).
m...@kernel.org is the canonical address.
> > Signed-off-by: Richard Henderson
> > ---
> >
> > Hi Mark, I think thi
;
> Reported-by: Vitaly Chikunov
> Signed-off-by: Peter Maydell
Acked-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Sat, 13 Aug 2022 12:11:37 +0100,
Vitaly Chikunov wrote:
>
> Marc,
>
> On Fri, Aug 12, 2022 at 04:02:37PM +0100, Marc Zyngier wrote:
> > On Fri, 12 Aug 2022 10:25:55 +0100,
> > Peter Maydell wrote:
> > >
> > > I've added some more relevant m
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get many errors l
Hi Peter,
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get ma
Hi Gavin,
On Thu, 11 Aug 2022 06:32:36 +0100,
Gavin Shan wrote:
>
> Hi Marc,
>
> On 8/8/22 7:17 PM, Marc Zyngier wrote:
> > On Wed, 03 Aug 2022 14:02:04 +0100,
> > Gavin Shan wrote:
[...]
> Sorry for the delay. I think the original changelog is confusing
> eno
On Wed, 03 Aug 2022 14:02:04 +0100,
Gavin Shan wrote:
>
> Hi Marc,
>
> On 8/3/22 5:01 PM, Marc Zyngier wrote:
> > On Wed, 03 Aug 2022 04:01:04 +0100,
> > Gavin Shan wrote:
> >> On 8/2/22 7:41 PM, Eric Auger wrote:
> >>> On 8/2/22 08:45, Gavin Shan
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
>
> Hi Eric,
>
> On 8/2/22 7:41 PM, Eric Auger wrote:
> > On 8/2/22 08:45, Gavin Shan wrote:
> >> There are 3 highmem IO regions as below. They can be disabled in
> >> two situations: (a) The specific region is disabled by user. (b)
> >> The
On Wed, 13 Jul 2022 07:02:10 +0100,
"chenxiang (M)" wrote:
>
> Hi Marc,
>
> Thank you for your reply.
>
> 在 2022/7/12 23:25, Marc Zyngier 写道:
> > Hi Xiang,
> >
> > On Tue, 12 Jul 2022 13:55:16 +0100,
> > "chenxiang (M)" wrote
Hi Xiang,
On Tue, 12 Jul 2022 13:55:16 +0100,
"chenxiang (M)" wrote:
>
> Hi,
> I encounter a issue related to GICv4 enable on ARM64 platform (kernel
> 5.19-rc4, qemu 6.2.0):
> We have a accelaration module whose VF has 3 MSI interrupts, and we
> passthrough it to virtual machine with following s
On Thu, 23 Jun 2022 14:10:17 +0100,
Andrew Jones wrote:
>
> As a side effect of leaving Red Hat I won't be able to use my Red Hat
> email address anymore. I'm also changing the name of my gitlab group.
>
> Signed-off-by: Andrew Jones
> Signed-off-by: Andrew Jo
On 2022-04-12 03:10, Atish Patra wrote:
The seria-pci device doesn't support MSI. Enable the device to provide
MSI so that any platform with MSI support only can also use
this serial device. MSI can be enabled by enabling the newly introduced
device property. This will be disabled by default pres
report in the dtb that the PSCI
implementation is 1.0-compatible if appropriate. (The device tree
binding currently only distinguishes "pre-0.2", "0.2-compatible" and
"1.0-compatible".)
Signed-off-by: Peter Maydell
Reviewed-by: Marc Zyngier
M.
--
Who you jivin' with that Cosmik Debris?
[+ Alex for HVF]
On Sun, 13 Feb 2022 05:05:33 +,
Akihiko Odaki wrote:
>
> On 2022/01/20 21:36, Peter Maydell wrote:
> > From: Marc Zyngier
> >
> > Even when the VM is configured with highmem=off, the highest_gpa
> > field includes devices that are above
On 2022-01-26 02:59, Philippe Mathieu-Daudé via wrote:
Hi,
On 26/1/22 00:59, Kenneth Adam Miller wrote:
Hello all,
I would like to emulate something on a pi so that I don't have to
pay as high of a translation penalty since the guest and host will
share the same arch. I'm finding that on som
Now that the devices present in the extended memory map are checked
against the available PA space and disabled when they don't fit,
there is no need to keep the same checks against highmem, as
highmem really is a shortcut for the PA space being 32bit.
Reviewed-by: Eric Auger
Signed-off-by:
Just like we can control the enablement of the highmem PCIe ECAM
region using highmem_ecam, let's add a control for the highmem
PCIe MMIO region.
Similarily to highmem_ecam, this region is disabled when highmem
is off.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zy
range, as the reported IPA space is larger than
what it should be.
Instead, honor the user-specified limit to only use the devices
at the lowest end of the spectrum, and fail if we have memory
crossing the 4GiB limit.
Reviewed-by: Andrew Jones
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
-off-by: Marc Zyngier
---
hw/arm/virt.c | 64 +--
1 file changed, 52 insertions(+), 12 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ecc3e3e5b0..a427676b50 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1660,7 +1660,7 @@ static
ck before we compute the memory map
- Drop useless MAX() when computing highest_gpa
- Fixed more deviations from the QEMU coding style
- Collected Eric's RBs, with thanks
[1]: https://lore.kernel.org/r/20220107163324.2491209-1-...@kernel.org
Marc Zyngier (6):
hw/arm/virt: Add a co
In order to only keep the highmem devices that actually fit in
the PA range, check their location against the range and update
highest_gpa if they fit. If they don't, mark them as disabled.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 34 --
1 file change
On Tue, 11 Jan 2022 13:58:49 +,
Peter Maydell wrote:
>
> On Sat, 8 Jan 2022 at 13:42, Marc Zyngier wrote:
> >
> > On 2022-01-07 20:23, Richard Henderson wrote:
> > > On 1/7/22 7:01 AM, Marc Zyngier wrote:
> > >> @@ -1380,17 +1380,10 @@ voi
Hi Michael,
On Sun, 09 Jan 2022 17:49:19 +,
"Michael S. Tsirkin" wrote:
>
> Fixes a couple of issues with irqfd use by config interrupt:
> - Rearrange initialization so cleanup happens in the reverse order
> - Don't use irqfd for config when not in use for data path
> I am not sure this is a
On Mon, 10 Jan 2022 17:12:50 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 1/7/22 5:33 PM, Marc Zyngier wrote:
> > In order to only keep the highmem devices that actually fit in
> > the PA range, check their location against the range and update
> > highest_gpa if
On Mon, 10 Jan 2022 15:47:47 +,
Peter Maydell wrote:
>
> On Mon, 10 Jan 2022 at 15:45, Marc Zyngier wrote:
> > $ /home/maz/vminstall/qemu-hack -m 1G -smp 256 -cpu host -machine
> > virt,accel=kvm,gic-version=3,highmem=on -nographic -drive
> > if=pflash,format=r
On Mon, 10 Jan 2022 15:38:56 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 1/7/22 5:33 PM, Marc Zyngier wrote:
> > The highmem attribute is nothing but another way to express the
> > PA range of a VM. To support HW that has a smaller PA range then
> > what QEMU assu
Hi Eric,
On Mon, 10 Jan 2022 15:35:44 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 1/7/22 5:33 PM, Marc Zyngier wrote:
[...]
> > @@ -190,7 +191,8 @@ static inline int
> > virt_gicv3_redist_region_count(VirtMachineState *vms)
> >
> > assert(vm
On 2022-01-07 20:23, Richard Henderson wrote:
On 1/7/22 7:01 AM, Marc Zyngier wrote:
@@ -1380,17 +1380,10 @@ void arm_cpu_finalize_features(ARMCPU *cpu,
Error **errp)
return;
}
-/*
- * KVM does not support modifications to this feature.
- * We
On Fri, 07 Jan 2022 18:48:16 +,
Peter Maydell wrote:
>
> On Fri, 7 Jan 2022 at 18:18, Marc Zyngier wrote:
> > This is a chicken and egg problem: you need the IPA size to compute
> > the memory map, and you need the memory map to compute the IPA
> > size. Fun, isn
Hi Eric,
On Fri, 07 Jan 2022 17:15:19 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 1/6/22 10:26 PM, Marc Zyngier wrote:
> > On Wed, 05 Jan 2022 09:22:39 +,
> > Eric Auger wrote:
> >> Hi Marc,
> >>
> >> On 12/27/21 10:16 PM, Marc Zyngi
In order to only keep the highmem devices that actually fit in
the PA range, check their location against the range and update
highest_gpa if they fit. If they don't, mark them them as disabled.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 34 --
1
Now that the devices present in the extended memory map are checked
against the available PA space and disabled when they don't fit,
there is no need to keep the same checks against highmem, as
highmem really is a shortcut for the PA space being 32bit.
Signed-off-by: Marc Zyngier
---
h
Just like we can control the enablement of the highmem PCIe ECAM
region using highmem_ecam, let's add a control for the highmem
PCIe MMIO region.
Similarily to highmem_ecam, this region is disabled when highmem
is off.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c
range, as the reported IPA space is larger than
what it should be.
Instead, honor the user-specified limit to only use the devices
at the lowest end of the spectrum, and fail if we have memory
crossing the 4GiB limit.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 10
-off-by: Marc Zyngier
---
hw/arm/virt.c | 53 ---
1 file changed, 46 insertions(+), 7 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 57c55e8a37..db4b0636e1 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1660,7 +1660,7 @@ static
can use the highmem redist
and PCIe ECAM ranges, but not the high PCIe range.
- Dropped some of Andrew's RBs, as the code significantly changed.
[1] https://lore.kernel.org/r/20211227211642.994461-1-...@kernel.org
Marc Zyngier (6):
hw/arm/virt: Add a control for the the highmem PCIe
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zy
;pauth' comment is removed from cpu-features.rst,
as it is now common to both TCG and KVM.
Tested on an Apple M1 running 5.16-rc6.
Cc: Eric Auger
Cc: Richard Henderson
Cc: Peter Maydell
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
* From v2:
- Fixed indentation and s
On Wed, 05 Jan 2022 09:22:39 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 12/27/21 10:16 PM, Marc Zyngier wrote:
> > Even when the VM is configured with highmem=off, the highest_gpa
> > field includes devices that are above the 4GiB limit.
> > Similarily, nothing
Hi Eric,
On Wed, 05 Jan 2022 09:41:19 +,
Eric Auger wrote:
>
> couldn't you simply introduce highmem_redist which is truly missing. You
> could set it in virt_set_memmap() in case you skip extended_map overlay
> and use it in virt_gicv3_redist_region_count() as you did?
> In addition to the
On Thu, 06 Jan 2022 18:26:29 +,
Richard Henderson wrote:
>
> Mm. It does beg the question of why KVM exposes multiple bits. If
> they must be tied, then it only serves to make the interface more
> complicated than necessary. We would be better served to have a
> single bit to control all o
On Thu, 06 Jan 2022 17:20:33 +,
Richard Henderson wrote:
>
> On 1/6/22 1:16 AM, Marc Zyngier wrote:
> >>> +static bool kvm_arm_pauth_supported(void)
> >>> +{
> >>> +return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS)
>
Hi Richard,
On Wed, 05 Jan 2022 21:36:55 +,
Richard Henderson wrote:
>
> On 1/3/22 10:05 AM, Marc Zyngier wrote:
> > -/*
> > - * KVM does not support modifications to this feature.
> > - * We have not registered the cpu properties when KVM
&
Hi Eric,
On Tue, 04 Jan 2022 15:31:33 +,
Eric Auger wrote:
>
> Hi Marc,
>
> On 12/27/21 4:53 PM, Marc Zyngier wrote:
> > Hi Eric,
> >
> > Picking this up again after a stupidly long time...
> >
> > On Mon, 04 Oct 2021 13:00:21 +0100,
> > Er
Hi Andrew,
On Mon, 03 Jan 2022 13:46:01 +,
Andrew Jones wrote:
>
> Hi Marc,
>
> On Tue, Dec 28, 2021 at 06:23:47PM +, Marc Zyngier wrote:
> > Add basic support for Pointer Authentication when running a KVM
> > guest and that the host supports it, loosely base
;pauth' comment is removed from cpu-features.rst,
as it is now common to both TCG and KVM.
Tested on an Apple M1 running 5.16-rc6.
Cc: Eric Auger
Cc: Andrew Jones
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Marc Zyngier
---
* From v1:
- Drop 'pauth' documentation
n an Apple M1 running 5.16-rc6.
Cc: Eric Auger
Cc: Andrew Jones
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Marc Zyngier
---
docs/system/arm/cpu-features.rst | 5 +
target/arm/cpu.c | 1 +
target/arm/cpu.h | 1 +
target/arm/cpu64.c
-off-by: Marc Zyngier
---
hw/arm/virt.c | 64 ---
1 file changed, 50 insertions(+), 14 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 84dd3b36fb..212079e7a6 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1660,10 +1660,10 @@ static
27;s 89f3bfa326
- Collected Andrew's RBs, with thanks
[1] https://lore.kernel.org/r/20211003164605.3116450-1-...@kernel.org
Marc Zyngier (5):
hw/arm/virt: Key enablement of highmem PCIe on highmem_ecam
hw/arm/virt: Add a control for the the highmem redistributors
hw/arm/virt: Honor
Currently, the highmem PCIe region is oddly keyed on the highmem
attribute instead of highmem_ecam. Move the enablement of this PCIe
region over to highmem_ecam.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c | 10 --
hw/arm/virt.c| 4
range, as the reported IPA space is larger than
what it should be.
Instead, honor the user-specified limit to only use the devices
at the lowest end of the spectrum, and fail if we have memory
crossing the 4GiB limit.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 9
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zy
Make sure both the highmem PCIe and GICv3 regions are disabled when
they don't fully fit in the PA range.
Reviewed-by: Andrew Jones
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 212079e7a6..18e61
On Mon, 04 Oct 2021 11:11:10 +0100,
Andrew Jones wrote:
>
> On Sun, Oct 03, 2021 at 05:46:04PM +0100, Marc Zyngier wrote:
> > The highmem attribute is nothing but another way to express the
> > PA range of a VM. To support HW that has a smaller PA range then
> > what QE
On Mon, 04 Oct 2021 13:23:41 +0100,
Eric Auger wrote:
>
> Hi Marc,
>
> On 10/3/21 6:46 PM, Marc Zyngier wrote:
> > Even when the VM is configured with highmem=off, the highest_gpa
> > field includes devices that are above the 4GiB limit.
> > Similarily, nothing se
Hi Eric,
Picking this up again after a stupidly long time...
On Mon, 04 Oct 2021 13:00:21 +0100,
Eric Auger wrote:
>
> Hi Marc,
>
> On 10/3/21 6:46 PM, Marc Zyngier wrote:
> > Currently, the highmem PCIe region is oddly keyed on the highmem
> > attribute instead o
any other interrupt,
and is quite happy to carry an active bit that eventually gets exposed
to the hypervisor.
I don't think this ever caused any issue, but I'd be pretty happy to
see the QEMU implementation fixed.
For the whole series:
Reviewed-by: Marc Zyngier
Thanks,
M.
Make sure both the highmem PCIe and GICv3 regions are disabled when
they don't fully fit in the PA range.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a572e0c9d9..756f67b6c8 100644
--- a/hw/arm/v
range, as the reported IPA space is larger than
what it should be.
Instead, honor the user-specified limit to only use the devices
at the lowest end of the spectrum, and fail if we have memory
crossing the 4GiB limit.
Signed-off-by: Marc Zyngier
---
hw/arm/virt.c | 9 -
1 file changed
ghmem PCIe and GICv3 RDs when they are outside of the
PA range
This has been tested on an M1-based Mac-mini running Linux v5.15-rc3.
[1] https://lore.kernel.org/r/2021082211.1290891-1-...@kernel.org
Marc Zyngier (5):
hw/arm/virt: Key enablement of highmem PCIe on highmem_ecam
hw/arm/v
Currently, the highmem PCIe region is oddly keyed on the highmem
attribute instead of highmem_ecam. Move the enablement of this PCIe
region over to highmem_ecam.
Signed-off-by: Marc Zyngier
---
hw/arm/virt-acpi-build.c | 10 --
hw/arm/virt.c| 4 ++--
2 files changed, 6
-off-by: Marc Zyngier
---
hw/arm/virt.c | 46 +++---
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9d2abdbd5f..a572e0c9d9 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1610,10 +1610,10 @@ static
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