[Qemu-devel] [PATCH v3] target-arm: implement LDA/STL instructions

This adds support for the ARMv8 load acquire/store release instructions. Since qemu does nothing special for memory barriers, these can be emulated like their non-acquire/release counterparts. Signed-off-by: Mans Rullgard --- Fixed issues found in v2. Could use more testing. --- target-arm

[Qemu-devel] [PATCH] target-arm: implement ARMv8 VSEL instruction

This adds support for the VSEL instruction introduced in ARMv8. It resides along with other new VFP instructions under the CDP2 encoding which was previously unused. Signed-off-by: Mans Rullgard --- Basic testing performed but not every combination. --- target-arm/translate.c | 51

[Qemu-devel] [PATCH v2] target-arm: implement LDA/STL instructions

This adds support for the ARMv8 load acquire/store release instructions. Since qemu does nothing special for memory barriers, these can be emulated like their non-acquire/release counterparts. Signed-off-by: Mans Rullgard --- Not thoroughly tested. --- target-arm/translate.c | 126

[Qemu-devel] [PATCH] target-arm: decode TBB/TBH more thoroughly

This avoids other opcodes being incorrectly decoded as TBB/TBH. The LDA/STL instructions new in ARMv8 use this space. Signed-off-by: Mans Rullgard --- This was previously sent as part of the LDA/STL patch. Separating it seems clearer. --- target-arm/translate.c | 2 +- 1 file changed, 1

[Qemu-devel] [PATCH v2] target-arm: add feature flag for ARMv8

Signed-off-by: Mans Rullgard --- Make V8 imply ARM_DIV and LPAE. --- target-arm/cpu.c | 7 ++- target-arm/cpu.h | 1 + target-arm/translate.c | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 496a59f..b75f396 100644

[Qemu-devel] [PATCH 2/3] target-arm: implement LDA/STL instructions

This adds support for the ARMv8 load acquire/store release instructions. Since qemu does nothing special for memory barriers, these can be emulated like their non-acquire/release counterparts. Signed-off-by: Mans Rullgard --- target-arm/translate.c | 91

[Qemu-devel] [PATCH 3/3] target-arm: explicitly decode SEVL instruction

The ARMv8 SEVL instruction is in the architectural hint space already emulated as nop. This makes the decoding of SEVL explicit for clarity. Signed-off-by: Mans Rullgard --- target-arm/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/translate.c b/target-arm

[Qemu-devel] [PATCH 1/3] target-arm: add feature flag for ARMv8

Signed-off-by: Mans Rullgard --- target-arm/cpu.c | 5 - target-arm/cpu.h | 1 + target-arm/translate.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 496a59f..f5a1314 100644 --- a/target-arm/cpu.c +++ b/target-arm