[PATCH v5 14/15] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20

[PATCH v5 09/15] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v5 13/15] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 8 ++--- target

[PATCH v5 12/15] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp

[PATCH v5 04/15] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 target/ppc/helper.h | 1 + target/ppc/insn32.decode

[PATCH v5 01/15] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecn

[PATCH v5 07/15] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 52 + target/ppc/helper.h | 1 + target/ppc/insn32

[PATCH v5 10/15] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 31 ++-- target/ppc/translate/dfp-impl.c.inc | 56

[PATCH v5 00/15] target/ppc: DFP instructions using decodetree

decNumberIntegralToInt128 Changes in v2: - Renamed abs64() to uabs64() Bruno Larsen (1): target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c Fernando Valle (1): target/ppc: Introduce REQUIRE_FPU Luis Pires (13): libdecnumber: introduce decNumberFrom[U]Int128 target/ppc: Implement DCFFIXQ

[PATCH v5 06/15] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c

[PATCH v5 08/15] target/ppc: Do not update nip on DFP instructions

Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate/dfp-impl.c.inc | 8 1 file changed, 8 deletions(-) diff --git a/targe

[PATCH v5 15/15] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v5 03/15] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2fafebd1c..48a484eef6 100644 --- a/target

[PATCH v5 05/15] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index a3a7ced78d..ca979dc6cc 100644 --- a/include/qemu/host

[PATCH v5 11/15] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode

[PATCH v5 02/15] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v4 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v4 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20

[PATCH v4 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 8 ++--- target

[PATCH v4 11/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 52 + target/ppc/helper.h | 1 + target/ppc/insn32

[PATCH v4 10/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c

[PATCH v4 09/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index a3a7ced78d..ca979dc6cc 100644 --- a/include/qemu/host

[PATCH v4 07/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2fafebd1c..48a484eef6 100644 --- a/target

[PATCH v4 06/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v4 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode

[PATCH v4 16/19] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp

[PATCH v4 05/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecn

[PATCH v4 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 31 ++-- target/ppc/translate/dfp-impl.c.inc | 56

[PATCH v4 12/19] target/ppc: Do not update nip on DFP instructions

Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires --- target/ppc/translate/dfp-impl.c.inc | 8 1 file changed, 8 deletions(-) diff --git a/target/ppc/translate/dfp-impl.c.i

[PATCH v4 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v4 04/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests

[PATCH v4 01/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v4 03/19] host-utils: add 128-bit quotient support to divu128/divs128

These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h

[PATCH v4 08/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 target/ppc/helper.h | 1 + target/ppc/insn32.decode

[PATCH v4 02/19] host-utils: move udiv_qrnnd() to host-utils

Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/fpu/softfloat-macros.h | 82 -- include/qemu/host-utils.h | 81

[PATCH v4 00/19] target/ppc: DFP instructions using decodetree

line' from times_* functions in ppc/translate.c - Used uadd64_overflow in mulu128 - Removed unnecessary 'else' from decNumberIntegralToInt128 Changes in v2: - Renamed abs64() to uabs64() Bruno Larsen (1): target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c Fernando Valle (1)

[PATCH v3 19/22] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp-impl.c.inc | 52

[PATCH v3 17/22] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 20 +- target/ppc/helper.h | 20 +- target/ppc/insn32.decode| 31 +++- target/ppc/translate/dfp-impl.c.inc | 57

[PATCH v3 15/22] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 53 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 5 +++ target

[PATCH v3 22/22] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 16 - target/ppc

[PATCH v3 21/22] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode

[PATCH v3 10/22] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v3 16/22] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 8

[PATCH v3 18/22] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode| 29 +++ target

[PATCH v3 09/22] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecn

[PATCH v3 12/22] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 11 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 8 target/ppc

[PATCH v3 14/22] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c

[PATCH v3 07/22] host-utils: add 128-bit quotient support to divu128/divs128

These will be used to implement new decimal floating point instructions from Power ISA 3.1. A new argument, prem, was added to divu128/divs128 to receive the remainder, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires --- include/hw/clock.h| 8

[PATCH v3 08/22] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 5736d285b2

[PATCH v3 13/22] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index eee58c0874..8360146979 100644 --- a/include/qemu/host

[PATCH v3 06/22] host-utils: move udiv_qrnnd() to host-utils

Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires --- include/fpu/softfloat-macros.h | 82 -- include/qemu/host-utils.h | 81 + 2 files changed, 81

[PATCH v3 20/22] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 8 ++--- target/ppc/helper.h | 8

[PATCH v3 11/22] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4749ecdaa9..5489b4b6e0 100644 --- a/target

[PATCH v3 01/22] host-utils: Fix overflow detection in divu128()

The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- util/host-utils.c | 2 +- 1 file changed, 1 inser

[PATCH v3 04/22] i386/kvm: Replace abs64() with uabs64() from host-utils

Drop abs64() and use uabs64() from host-utils, which avoids an undefined behavior when taking abs of the most negative value. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Reviewed-by: Eduardo Habkost --- hw/i386/kvm/i8254.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions

[PATCH v3 02/22] host-utils: fix missing zero-extension in divs128

*plow (lower 64 bits of the dividend) is passed into divs128() as a signed 64-bit integer. When building an __int128_t from it, it must be zero-extended, instead of sign-extended. Suggested-by: Richard Henderson Signed-off-by: Luis Pires --- include/qemu/host-utils.h | 2 +- 1 file changed, 1

[PATCH v3 03/22] host-utils: introduce uabs64()

Introduce uabs64(), a function that returns the absolute value of a 64-bit int as an unsigned value. This avoids the undefined behavior for common abs implementations, where abs of the most negative value is undefined. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Reviewed-by

[PATCH v3 05/22] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v3 00/22] target/ppc: DFP instructions using decodetree

divu128/divs128 target/ppc: Implement DCFFIXQQ target/ppc: Implement DCTFIXQQ target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html> Bruno Larsen (1):

[PATCH v2 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 8 ++--- target/ppc/helper.h | 8

[PATCH v2 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode| 29 +++ target

[PATCH v2 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 16 - target/ppc

[PATCH v2 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 20 +- target/ppc/helper.h | 20 +- target/ppc/insn32.decode| 31 +++- target/ppc/translate/dfp-impl.c.inc | 57

[PATCH v2 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode

[PATCH v2 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 8

[PATCH v2 16/19] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp-impl.c.inc | 52

[PATCH v2 12/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 53 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 5 +++ target

[PATCH v2 07/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 target/ppc/translate/vector

[PATCH v2 11/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c | 94 +

[PATCH v2 10/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires --- include/qemu/host-utils.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 6f18b29921..9f40077083 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host

[PATCH v2 05/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 185 +++ 2 files changed, 186 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 5736d285b2

[PATCH v2 08/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: David Gibson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4749ecdaa9..5489b4b6e0 100644 --- a/target/ppc

[PATCH v2 09/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 11 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 8 target/ppc

[PATCH v2 04/19] host-utils: add 128-bit quotient support to divu128/divs128

mproved, due to the smaller number of shift-subtract iterations. Signed-off-by: Luis Pires --- include/hw/clock.h| 8 +-- include/qemu/host-utils.h | 20 -- target/ppc/int_helper.c | 13 ++-- util/host-utils.c | 128 +++--- 4 files

[PATCH v2 02/19] host-utils: move abs64() to host-utils as uabs64()

Move abs64 to host-utils as uabs64, so it can be used elsewhere. The function was renamed to uabs64 and modified to return an unsigned value. This avoids the undefined behavior for common abs implementations, where abs of the most negative value is undefined. Signed-off-by: Luis Pires --- hw

[PATCH v2 03/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v2 06/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecnumber/decNumber.h b/in

[PATCH v2 01/19] host-utils: Fix overflow detection in divu128()

The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires --- util/host-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PATCH v2 00/19] target/ppc: DFP instructions using decodetree

umberFrom[U]Int128 target/ppc: Implement DCFFIXQQ host-utils: Introduce mulu128 libdecnumber: Introduce decNumberIntegralToInt128 target/ppc: Implement DCTFIXQQ target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal -

[PATCH 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 16 - target/ppc/helper.h | 16

[PATCH 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 8 ++--- target/ppc/helper.h | 8 ++--- target/ppc/insn32.decode

[PATCH 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 23 target

[PATCH 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 8 +++ target/ppc/helper.h | 8

[PATCH 11/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c | 94 +

[PATCH 16/19] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp-impl.c.inc | 52 + target/ppc/translate

[PATCH 10/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires --- include/qemu/host-utils.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 8e8cab9a3e..2e3b5ad989 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host

[PATCH 09/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 11 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 8 target/ppc

[PATCH 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires --- target/ppc/dfp_helper.c | 20 +- target/ppc/helper.h | 20 +- target/ppc/insn32.decode| 31 +++- target/ppc/translate/dfp-impl.c.inc | 57 ++--- target/ppc/translate/dfp-ops.c.inc | 19

[PATCH 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode| 29 +++ target

[PATCH 07/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 target/ppc/translate/vector

[PATCH 08/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4749ecdaa9..5489b4b6e0 100644 --- a/target/ppc/translate.c +++ b/target/ppc

[PATCH 12/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 53 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 5 +++ target

[PATCH 03/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH 05/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 185 +++ 2 files changed, 186 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 5736d285b2

[PATCH 06/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecnumber/decNumber.h b/in

[PATCH 02/19] host-utils: move abs64() to host-utils

Move abs64 to host-utils so it can be reused elsewhere. Also made it inline. Signed-off-by: Luis Pires --- hw/i386/kvm/i8254.c | 5 - include/qemu/host-utils.h | 8 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c index

[PATCH 04/19] host-utils: add 128-bit quotient support to divu128/divs128

mproved, due to the smaller number of shift-subtract iterations. Signed-off-by: Luis Pires --- include/hw/clock.h| 8 +-- include/qemu/host-utils.h | 20 -- target/ppc/int_helper.c | 13 ++-- util/host-utils.c | 128 +++--- 4 files

[PATCH 01/19] host-utils: Fix overflow detection in divu128()

The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires --- util/host-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PATCH 00/19] target/ppc: DFP instructions using decodetree

patch series. Based-on: 20210823150235.35759-1-luis.pi...@eldorado.org.br (target/ppc: fix setting of CR flags in bcdcfsq) -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html> Bruno Larsen (1): target/ppc: Move REQUIR

[PATCH] target/ppc: fix setting of CR flags in bcdcfsq

all zero. This would happen for source values of +/-10^31, +/-10^32, etc. The new implementation fixes this and also skips the result calculation altogether in case of src overflow. Signed-off-by: Luis Pires --- target/ppc/int_helper.c | 61 - 1 file

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