The register request via gdbstub would return the SR part
which contains the Trace/Master/IRQ state flags, but
would be missing the CR (Condition Register) state bits.
This fix adds this support by merging them in the m68k
specific gdbstub handler
Signed-off-by: Lucien Murray-Pitts
---
target/m
A regression that was introduced, with the refactor to TranslatorOps,
drops two lines that update the PC when single-stepping is being performed.
( short commit 11ab74b )
This patch resolves that issue.
Signed-off-by: Lucien Murray-Pitts
---
target/m68k/translate.c | 2 ++
1 file changed, 2 ins
On CPU32 and the early 68000 and 68010 the ISP doesnt exist.
These CPUs only have SSP/USP.
The availability of this feature is determined by the
implementation of Master mode bit in the SR register.
Those with the master-mode bit have ISP.
Additional comments added to the features set to claify
This fixes a regression in rsp packet vCont, this was due to the
recently added multiprocess support. (Short commit hash: e40e520).
The result is that vCont now does not recognise the case where
no process/thread is provided after the action.
This may not show up with GDB, but using Lauterbach Tr
The result is that vCont now does not recognise the case where no
process/thread is provided after the action.
This may not show up with GDB, but using Lauterbach Trace32, and Hexrays IDA
Pro this issue is immediately seen.
The response is a "$#00" empty packet, showing it is unsupported packet.
