GIC is stored in the intc array. When connecting an IRQ,
a TYPE_SPLIT_IRQ device is created with its num-lines property set to
the number of GICs in the SoC. The split device is used to fan out the
IRQ to all the GICs.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 1 +
hw/arm/xlnx
Refactore the eFuse devices creation using the VersalMap structure.
Note that the corresponding FDT nodes are removed. They do not
correspond to any real node in standard Versal DTBs. No matching drivers
exist for them.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 +--
hw
From: Francisco Iglesias
Introduce a 'first-cpu-index' property for specifying the first QEMU CPU
connected to the GICv3. This makes it possible to have multiple instances
of the GICv3 connected to different CPU clusters.
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
controller
advertised by the SoC.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 7 +--
hw/arm/xlnx-versal-virt.c| 73 ++
hw/arm/xlnx-versal.c | 86 +---
3 files changed, 87 insertions(+), 79 deletions(-)
diff --git a
Drop unused include directives from xlnx-versal-crl.c
Signed-off-by: Luc Michel
---
hw/misc/xlnx-versal-crl.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
index 08ff2fcc24f..f288545967a 100644
--- a/hw/misc/xlnx
Refactor the PMC IOU SLCR device creation using the VersalMap structure.
This is the first user of a shared IRQ using an OR gate. The OSPI
controller is reconnected to the SLCR.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5
hw/arm/xlnx-versal.c | 48
Refactor the OCM creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 4
hw/arm/xlnx-versal.c | 20
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm
Add the instance of the GIC ITS in the APU.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 50
1 file changed, 50 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 35c32de0159..ba8c69bd435 100644
--- a/hw/arm/xlnx
Refactor the OSPI controller creation using the VersalMap structure.
Note that the connection to the PMC IOU SLCR is removed for now and will
be re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 12 +--
hw/arm/xlnx-versal-virt.c| 41 --
hw/arm
Versal SoC. It also fixes a bug where the gem device pointer
was mapped to the usb link property.
Signed-off-by: Luc Michel
---
include/hw/misc/xlnx-versal-crl.h | 8 +-
hw/misc/xlnx-versal-crl.c | 163 --
2 files changed, 92 insertions(+), 79 deletions(-)
diff
Refactor the RTC device creation using the VersalMap structure.
The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1
(addr error IRQ). This does not change the current behaviour since the
RTC model does not implement those IRQs anyway.
Signed-off-by: Luc Michel
---
include/hw
Use the bsa.h header for ARM timer and maintainance IRQ indices instead
of redefining our owns.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 6 --
hw/arm/xlnx-versal.c | 28 +---
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git
provide a DTB.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 49
hw/arm/xlnx-versal-virt.c| 37 +++--
2 files changed, 76 insertions(+), 10 deletions(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs
Refactor the CPU cluster creation using the VersalMap structure. There
is no functional change. The clusters properties are now described in
the VersalMap structure. For now only the APU is converted. The RPU will
be taken care of by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm
Add a test for the amd-versal2-virt machine using the same command line,
kernel, initrd than the ones used for amd-versal-virt.
Signed-off-by: Luc Michel
---
tests/functional/test_aarch64_xlnx_versal.py | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tests
Add support for GICv2 instantiation in the Versal SoC. This is in
preparation for the RPU refactoring.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 82 +---
1 file changed, 62 insertions(+), 20 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw
Refactor the RPU cluster creation using the VersalMap structure. This
effectively instantiate the RPU GICv2 which was not instantiated before.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 11 ---
hw/arm/xlnx-versal-virt.c| 1 +
hw/arm/xlnx-versal.c | 60
Remove now unused clock nodes. They have been replaced by the ones
created in the SoC. Remove the unused cfg.secure VersalVirt field.
Remove unecessary include directives.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal-virt.c | 24
1 file changed, 24 deletions
be left unconnected. This is in preparation for
versal2.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 41 +++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 9d900fe3127..551671af425
Refactor the ADMA creation using the VersalMap structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 -
hw/arm/xlnx-versal-virt.c| 28 --
hw/arm/xlnx-versal.c
Add a way to configure the MP affinity value of the CPUs given their
core and cluster IDs. For the Versal APU CPUs, the MP affinity value is
directly given by the core ID.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 21 +
1 file changed, 21 insertions(+)
diff --git
Add support for the ARM Cortex-A78AE CPU.
Signed-off-by: Luc Michel
---
target/arm/tcg/cpu64.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 35cddbafa4c..337f8cf0c8d 100644
--- a/target/arm
To align with current branding and ensure coherency with the upcoming
versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt.
Keep an alias of the old name to the new one for command-line backward
compatibility.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst
Split the xlnx-versal-virt machine type into a base abstract type and a
concrete type. There is no functional change. This is in preparation for
versal2 machine.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal-virt.c | 74 +++
1 file changed, 52 insertions
Update the list of supported devices in the Versal SoCs.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/system/arm/xlnx-versal-virt.rst
index 2c63fbf519f
Refactor the GEM ethernet controllers creation using the VersalMap
structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 -
hw/arm/xlnx-versal-virt.c| 54 -
hw
on the CRL.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 5151822ad56..796b4911a02 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx
Refactor the USB controller creation using the VersalMap structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 ---
hw/arm/xlnx-versal-virt.c| 56
only creates the two clock nodes. The ones from the
xlnx-versal virt machine are renamed with a `old-' prefix and will be
removed once they are not referenced anymore.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 12
hw/arm/xlnx-versal-virt.c| 11 +++---
Add a note in the DTB section explaining how to dump the generated DTB
using the dumpdtb machine option.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs
Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
is in preparation for the versal2 version of the CRL.
Signed-off-by: Luc Michel
---
include/hw/misc/xlnx-versal-crl.h | 31 ++--
hw/misc/xlnx-versal-crl.c | 48 +++
2
Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the
number of CPUs in the SoC. Use it in the xlnx-versal-virt machine.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 1 +
hw/arm/xlnx-versal-virt.c| 7 ---
hw/arm/xlnx-versal.c | 8
3 files
Refactor the DDR aperture regions creation using the VersalMap
structure. Device creation and FDT node creation are split into two
functions because the later must happen during ARM virtual bootloader
modify_dtb callback.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 7 +---
hw
Refactor the creation of virtio devices. Use the accessors provided by
the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
defined in the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +++
hw/arm/xlnx-versal-virt.c| 31
Add the versal2 version of the CRL device. For the implemented part, it
is similar to the versal version but drives reset line of more devices.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal-version.h | 1 +
include/hw/misc/xlnx-versal-crl.h| 329 ++
hw/misc
devices. An OR gate is
created to connect the devices to the actual IRQ pin.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index
Remove now unused macros in xlnx-versal.[ch]. Those macros have been
replaced by the VersalMap structure that serves as a central description
for the SoC. The ones still in use in the versal_unimp function are
inlined.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 204
Refactor the CFU device creation using the VersalMap structure. All
users of the APB IRQ OR gate have now been converted. The OR gate device
can be dropped.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 14 --
hw/arm/xlnx-versal.c | 258
Add the per_cluster_gic switch to the VersalCpuClusterMap structure.
When set, this indicates that a GIC instance should by created
per-cluster instead of globaly for the whole RPU or APU. This is in
preparation for versal2.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 15
almost fully describe the implemented parts of
versal2.
The versal2 eFuse device differs quite a lot from the versal one and is
left as future work.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 17 ++-
hw/arm/xlnx-versal.c | 212 ---
2 files
Refactor the CRL device creation using the VersalMap structure. The
connections to the RPU CPUs are temporarily removed and will be
reintroduced with next refactoring commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 ---
hw/arm/xlnx-versal.c | 36
Refactor the BBRAM device creation using the VersalMap structure.
Note that the corresponding FDT node is removed. It does not correspond
to any real node in standard Versal DTBs. No matching drivers exist for
it.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +--
hw/arm/xlnx
Refactor the TRNG device creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 --
hw/arm/xlnx-versal.c | 18 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw
Refactor the XRAM devices creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 6
hw/arm/xlnx-versal.c | 59 +---
2 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/xlnx
Split the xlnx-versal device into two classes, a base, abstract class
and the existing concrete one. Introduce a VersalVersion type that will
be used across several device models when versal2 implementation is
added.
This is in preparation for versal2 implementation.
Signed-off-by: Luc Michel
-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 -
hw/arm/xlnx-versal-virt.c| 36 +
hw/arm/xlnx-versal.c | 142 ---
3 files changed, 117 insertions(+), 63 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx
The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.
Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt
registers")
Signed-off-by: Luc Michel
---
hw/net/cadence
Refactor the SDHCI controllers creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 +-
hw/arm/xlnx-versal-virt.c| 43 ++--
hw/arm/xlnx-versal.c | 96
3 files changed, 83 insertions
.
Thanks
Luc
Francisco Iglesias (1):
hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property
Luc Michel (47):
hw/net/cadence_gem: fix register mask initialization
hw/arm/xlnx-versal: split the xlnx-versal type
hw/arm/xlnx-versal: prepare for FDT creation
hw/arm/xlnx-ve
splay a warning when this occurs.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/char/pl011.c b/hw/char/pl011.c
> in
es: 63242a007a1 ("SH4: Serial controller improvement")
> Signed-off-by: Philippe Mathieu-Daudé
nice one :)
Reviewed-by: Luc Michel
> ---
> hw/char/sh_serial.c | 30 ++
> 1 file changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/h
troduced in commit 20dcee94833 ("MCF5208 emulation"),
> we only read 1 char at a time!
"the MCF UART model"
Reviewed-by: Luc Michel
>
> Have the IOCanReadHandler handler return how many elements are
> available, and use that in the IOReadHandler handler.
>
>
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Defines FIFO_DEPTH and use it, fixing coding style.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/mcf_uart.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
&g
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> While we model a 32-elements RX FIFO since the PL011 model was
> introduced in commit 988f2442971 ("hw/char/imx_serial: Implement
> receive FIFO and ageing timer") we only read 1 char at a time!
"the IMX serial m
patch and the subsequent ones you keep
mentioning the PL011 model while you modify other UARTs. I guess you
mean "the BCM2835 AUX model" here?
In any case:
Reviewed-by: Luc Michel
>
> Have the IOCanReadHandler handler return how many elements are
> available, and use that in th
1_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars
> pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars
> pl011_read addr 0x018 value 0x0090 reg FR
> pl011_write addr 0x000 value 0x0072 reg DR
>
> Inspired-by: Peter Maydell
> Signed-off
Hi Phil,
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> We shouldn't receive characters when the full UART or its
> receiver is disabled. However we don't want to break the
> possibly incomplete "my first bare metal assembly program"s,
> so we choose to simply display a warning when thi
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Log FIFO use (availability and depth).
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 10 ++
> hw/char/trace-events | 7 ---
> 2 files changed
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Introduce 'fifo_depth' and 'fifo_available' local variables
> to better express the 'r' variable use.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/p
On 18:10 Tue 02 Jul , Philippe Mathieu-Daudé wrote:
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but has a
> vendor
On 11:43 Sat 22 Jun , Inès Varhol wrote:
> For USART, GPIO and SYSCFG devices, check that clock frequency before
> and after enabling the peripheral clock in RCC is correct.
>
> Signed-off-by: Inès Varhol
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
>
On 11:43 Sat 22 Jun , Inès Varhol wrote:
> This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
> corresponding clock from STM32L4x5 RCC.
>
> Signed-off-by: Inès Varhol
> Reviewed-by: Peter Maydell
> Reviewed-by: Philippe Mathieu-Daudé
Revie
On 09:00 Fri 28 Jun , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single blo
On 09:00 Fri 28 Jun , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
>
uot;trace.h"
>
> @@ -158,6 +160,15 @@ bool clock_set_mul_div(Clock *clk, uint32_t multiplier,
> uint32_t divider)
> return true;
> }
>
> +static void clock_period_prop_get(Object *obj, Visitor *v, const char *name,
> +
ht reset type for the ShutdownCause it is passed. This
> allows us to get rid of the device_reset_reason global we
> were using to implement qemu_register_reset_nosnapshotload().
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> docs/devel/reset.rst| 17 ++
't know
> about should be handled like RESET_TYPE_COLD"; switch these
> devices to do that. Then adding a new reset type will only
> need to touch those devices where its behaviour really needs
> to be different from the standard cold reset.
>
> Signed-off-by: Peter Mayde
--sp-file scripts/coccinelle/reset-type.cocci \
> --keep-comments --smpl-spacing --in-place \
> --include-headers --dir $dir; done
>
> and no manual edits.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> incl
On 17:08 Fri 12 Apr , Peter Maydell wrote:
> Update the reset documentation's example code to match the new API
> for the hold and exit phase method APIs where they take a ResetType
> argument.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
>
#x27;s reset method directly
>calls the implementation of a different device's method
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
(I'm not a coccinelle expert but LGTM)
> ---
> The structure here is a bit of an experiment: usually I would make
> the
ture for the hold and exit reset methods.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/i2c/allwinner-i2c.c | 3 +--
> hw/sensor/adm1272.c| 2 +-
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c
On 18:15 Sun 31 Mar , Stefan Weil wrote:
> Signed-off-by: Stefan Weil
Reviewed-by: Luc Michel
> ---
> docs/devel/atomics.rst | 2 +-
> docs/devel/ci-jobs.rst.inc | 2 +-
> docs/devel/clocks.rst | 2 +-
> docs/system/i386/sgx.rst | 2 +-
> qapi/qom.json
On 09:40 Mon 25 Mar , Luc Michel wrote:
> On 16:58 Fri 22 Mar , Philippe Mathieu-Daudé wrote:
> > Let clock_set_mul_div() return a boolean value whether the
> > clock has been updated or not, similarly to clock_set().
> >
> > Signed-off-by: Philippe Mathie
On 16:39 Fri 22 Mar , Peter Maydell wrote:
> On Fri, 22 Mar 2024 at 15:59, Philippe Mathieu-Daudé
> wrote:
> >
> > From: Arnaud Minier
> >
> > The "clock_set_mul_div" function doesn't propagate the clock period
> > to the children if it is changed (e.g. by enabling/disabling a clock
> > mult
On 16:58 Fri 22 Mar , Philippe Mathieu-Daudé wrote:
> Let clock_set_mul_div() return a boolean value whether the
> clock has been updated or not, similarly to clock_set().
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Luc Michel
> ---
> include/hw/clock.h |
On 14:33 Thu 29 Feb , Alex Bennée wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Luc Michel writes:
>
> > On 15:09 Tue 27 Feb , Pierrick Bouvier wrote:
>
On 14:56 Tue 27 Feb , Pierrick Bouvier wrote:
> Hi Luc,
>
> On 2/27/24 1:35 PM, Luc Michel wrote:
> > Hi Pierrick,
> >
> > On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> > > Signed-off-by: Pierrick Bouvier
>
On 15:09 Tue 27 Feb , Pierrick Bouvier wrote:
> On 2/27/24 2:54 PM, Luc Michel wrote:
> > Hi Pierrick,
> >
> > On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> > > Signed-off-by: Pierrick Bouvier
> > > ---
&
Hi Pierrick,
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
> ---
> contrib/plugins/hotblocks.c | 50 ++---
> 1 file changed, 30 insertions(+), 20 deletions(-)
>
> diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/hot
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
Reviewed-by: Luc Michel
> ---
> tests/plugin/bb.c | 63 +++
> 1 file changed, 26 insertions(+), 37 deletions(-)
>
> diff --git a/tests/plugin/b
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
Reviewed-by: Luc Michel
> ---
> tests/plugin/insn.c | 106 +---
> 1 file changed, 50 insertions(+), 56 deletions(-)
>
> diff --git a/tests/plugin/ins
Hi Pierrick,
On 13:14 Mon 26 Feb , Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
> ---
> tests/plugin/mem.c | 40 +---
> 1 file changed, 25 insertions(+), 15 deletions(-)
>
> diff --git a/tests/plugin/mem.c b/tests/plugin/mem.c
> index 44e9106
rt92.c| 1 +
> hw/isa/lpc_ich9.c | 1 -
> hw/timer/hpet.c | 1 -
> target/i386/monitor.c | 1 -
> 9 files changed, 8 insertions(+), 12 deletions(-)
>
> --
> 2.41.0
>
>
For the series:
Reviewed-by: Luc Michel
An access fault is raised when the Access Flag is not set in the
looked-up PTE and the AFFD field is not set in the corresponding context
descriptor. This was already implemented for stage 2. Implement it for
stage 1 as well.
Signed-off-by: Luc Michel
---
v2: drop erroneous submodule
An access fault is raised when the Access Flag is not set in the
looked-up PTE and the AFFD field is not set in the corresponding context
descriptor. This was already implemented for stage 2. Implement it for
stage 1 as well.
Signed-off-by: Luc Michel
---
hw/arm/smmuv3-internal.h | 1
s process works,
> or anything else that developers might need to know about
> how to add documentation.
>
> Make the .hx files refer to this doc file, and clean
> up their header comments to be more accurate for the
> usage in each file and less cut-n-pasted.
>
> Signed-off-by:
Hi,
On 20:13 Wed 13 Dec , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Hi Arnaud,
>
> (Cc'ing Peter and Luc)
>
> On 12/12/23 14:05, Arnaud Minier wrote:
> > Hi
On 19:58 Tue 14 Nov , Michael Tokarev wrote:
> Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register
> definitions"
> Cc: Luc Michel
> Cc: Peter Maydell
> Signed-off-by: Michael Tokarev
Reviewed-by: Luc Michel
> ---
> hw/net/cadence_gem.c
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/xlnx-zynqmp.h | 1 -
> hw/arm/xlnx-zcu102.c | 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx7.h | 1 -
> hw/arm/mcimx7d-sabre.c| 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/xlnx-versal.h | 1 -
> hw/arm/xlnx-versal-virt.c| 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx6ul.h | 1 -
> hw/arm/mcimx6ul-evk.c | 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx31.h | 1 -
> hw/arm/kzm.c | 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx6.h | 1 -
> hw/arm/sabrelite.c| 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-r40.h | 1 -
> hw/arm/bananapi_m2u.c
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-h3.h | 1 -
> hw/arm/orangepi.c | 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx25.h | 1 -
> hw/arm/imx25_pdk.c | 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-a10.h | 1 -
> hw/arm/cubieboard.c
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 955a8da134..4c5fe10316 100644
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 92 ++--
1 file changed, 47 insertions(+), 45 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0e5744ecd7
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