Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 4:10 p.m., Guenter Roeck wrote: > FWIW, I absoutely agree. If the board can only be used to boot an initrd, > it is quite pointless to have it around. Actually it is worse than pointless, > since it will result in people wasting their time trying to get it to work. As someone who

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 3:14 p.m., Alistair Francis wrote: >> and networking works? > > Yep, it should. This is for the -nic option [1]. I misunderstood when > I was going through it. > > We can drop this patch then. > > 1: > https://github.com/qemu/qemu/commit/fea9b3ca9cc4685f89e0b929a61e51098fbb4f49

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 3:09 p.m., Alistair Francis wrote: > Yeah, it's a real pain. I had a go at adding the SD card [1] but never > got it fully working. Normally I just hack in the virtIO MMIO regions > and use those. > > 1: https://github.com/alistair23/qemu/tree/mainline/alistair/sifive_spi.next >

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 3:16 p.m., Logan Gunthorpe wrote: > > > On 2018-11-21 3:14 p.m., Alistair Francis wrote: >>> and networking works? >> >> Yep, it should. This is for the -nic option [1]. I misunderstood when >> I was going through it. >> >>

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 2:55 p.m., Alistair Francis wrote: > It is required for networking for PCIe devices. What PCIe device works > for you without this patch? Can you tell me your command line > arguments. I can run it without that patch using a e1000e device and it works just fine. Command line: $Q

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 2:54 p.m., Alistair Francis wrote: > The last time I tested this it worked (although I might not have > tested interrupts) and now it doesn't. Nothing has changed in the > series, my guest software has changed though. I can see the root > complex, but no devices underneath it. > >

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 12:21 p.m., Alistair Francis wrote: > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe wrote: >> Well, I also have a kernel (one I've built myself) without microsemi >> support, but with Xilinx support and it also doesn't work (see my dmesg >>

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 12:18 p.m., Alistair Francis wrote: >>> >>> You should just be able to edit the source, grep for "microsemi". >> >> I don't see any "microsemi" in my riscv-pk source... > > msemi maybe? > > The compatible sting is: ms-pf,axi-pcie-host None of the above. Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 12:16 p.m., Alistair Francis wrote: >>> Do you see the MicroSemi PCIe probe in your dmesg? >> >> I do when I have a kernel with microsemi PCI Support (specifically the >> one included in the bbl you sent us a while back). > > Yeah, so you need to make sure that doesn't happen. We

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 12:02 p.m., Alistair Francis wrote: > On Wed, Nov 21, 2018 at 10:50 AM Logan Gunthorpe wrote: >> >> >> >> On 2018-11-21 11:32 a.m., Alistair Francis wrote: >>> That seems like either a kernel or bbl issue. >>> >>> You need

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:34 a.m., Alistair Francis wrote: >> I don't understand what this patch actually accomplishes. It doesn't >> seem to affect my network devices when running QEMU. Can you provide a >> commit message explaining this? > > Could you connect a PCIe networking device without this comm

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 12:02 p.m., Alistair Francis wrote: >> Ok, how do I stop bbl from editing the device tree? I have a kernel with >> Xilinx PCI support but it fails initializing on that machine (see below). > > You should just be able to edit the source, grep for "microsemi". Gross. > Do you see

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:59 a.m., Alistair Francis wrote: > On Wed, Nov 21, 2018 at 10:56 AM Logan Gunthorpe wrote: >> >> >> >> On 2018-11-21 11:49 a.m., Alistair Francis wrote: >>> Agreed. It's the same number as the last interrupt in the QEMU SiFive >

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:49 a.m., Alistair Francis wrote: > Agreed. It's the same number as the last interrupt in the QEMU SiFive > U machine. So that is where it came from. Ok, can we have a comment for that? Logan

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:36 a.m., Guenter Roeck wrote: > What kernel configuration, devicetree, and qemu command line do you use > for the sifive_u machine ? For kernel configuration, I've tried a couple but I've attached one that I think makes sense. The device tree is whatever bbl/qemu are doing (sou

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:32 a.m., Alistair Francis wrote: > That seems like either a kernel or bbl issue. > > You need to make sure that bbl doesn't edit the device tree (to add > the Microsemi device or remove the Xilinx one) and ensure your kernel > supports the Xilinx one. Ok, how do I stop bbl fro

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 11:17 a.m., Alistair Francis wrote: > On Wed, Nov 21, 2018 at 9:58 AM Logan Gunthorpe wrote: >> >> >> >> On 2018-11-21 10:02 a.m., Alistair Francis wrote: >>> Increase the number of interrupts to match the HiFive Unleashed board. >

Re: [Qemu-devel] [PATCH for-3.2 v7 3/6] hw/riscv/virt: Connect the gpex PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Signed-off-by: Alistair Francis > Signed-off-by: Logan Gunthorpe Reviewed-by: Logan Gunthorpe > diff --git a/default-configs/riscv32-softmmu.mak > b/default-configs/riscv32-softmmu.mak > index 7937c69e22..3e3d195f37

Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Connect the Xilinx PCIe device based on the information in the device > tree stored in the ROM of the HiFish Unleashed board. I only briefly tested this patch but could not get any PCI devices to come up with the sifive_u machine. Depending on

Re: [Qemu-devel] [PATCH for-3.2 v7 4/6] riscv: Enable VGA and PCIE_VGA

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Enable compile support for VGA devices. This allows the user to conenct > a display by adding '-device bochs-display -display sdl' to their > command line argument. > > Signed-off-by: Alistair Francis Rev

Re: [Qemu-devel] [PATCH for-3.2 v7 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:03 a.m., Alistair Francis wrote: > +pci_bus = PCI_HOST_BRIDGE(dev)->bus; > + > +for (i = 0; i < nb_nics; i++) { > +NICInfo *nd = &nd_table[i]; > + > +if (!nd->model) { > +nd->model = g_strdup("virtio"); > +} > + > +pci_nic_init_

[Qemu-devel] [PATCH] hw/block/nvme: fix bug with PCI IRQ pins on teardown

2018-11-21 Thread Logan Gunthorpe
host. Linux sees this as a long delay when unbinding the nvme device. Eventually the interrupt timeout occurs and it continues. To fix this we ensure we deassert the IRQ for a CQ when it is deleted. Signed-off-by: Logan Gunthorpe --- hw/block/nvme.c | 1 + 1 file changed, 1 insertion(+) diff

Re: [Qemu-devel] [PATCH for-3.2 v7 2/6] hw/riscv/virt: Adjust memory layout spacing

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Signed-off-by: Alistair Francis Reviewed-by: Logan Gunthorpe > --- > hw/riscv/virt.c | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c

Re: [Qemu-devel] [PATCH for-3.2 v7 1/6] hw/riscv/virt: Increase the number of interrupts

2018-11-21 Thread Logan Gunthorpe
On 2018-11-21 10:02 a.m., Alistair Francis wrote: > Increase the number of interrupts to match the HiFive Unleashed board. > > Signed-off-by: Alistair Francis > --- > include/hw/riscv/virt.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/riscv/virt.h b/in

Re: [Qemu-devel] [Qemu-block] [PATCH] Added iopmem device emulation

2016-11-08 Thread Logan Gunthorpe
Hey, On 08/11/16 08:58 AM, Stefan Hajnoczi wrote: > My concern with the current implementation is that a PCI MMIO access > invokes a synchronous blk_*() call. That can pause vcpu execution while > I/O is happening and therefore leads to unresponsive guests. QEMU's > monitor interface is also blo

Re: [Qemu-devel] [Qemu-block] [PATCH] Added iopmem device emulation

2016-11-07 Thread Logan Gunthorpe
Hey, On 07/11/16 03:28 AM, Stefan Hajnoczi wrote: > It may be too early to merge this code into qemu.git if there is no > hardware spec and this is a prototype device that is subject to change. Fair enough, though the interface is so simple I don't know what could possibly change. > I'm wonderin

Re: [Qemu-devel] [Qemu-block] [PATCH] Added iopmem device emulation

2016-11-04 Thread Logan Gunthorpe
Hi Stefan, On 04/11/16 04:49 AM, Stefan Hajnoczi wrote: > QEMU already has NVDIMM support (https://pmem.io/). It can be used both > for passthrough and fake non-volatile memory: > > qemu-system-x86_64 \ > -M pc,nvdimm=on \ > -m 1024,maxmem=$((4096 * 1024 * 1024)),slots=2 \ > -objec

[Qemu-devel] [PATCH] Added iopmem device emulation

2016-10-18 Thread Logan Gunthorpe
d BAR window. This patch creates an emulated device which helps to test and debug the kernel driver for iopmem while hardware availability is poor. A kernel patch for a driver is being prepared simultaneously. Signed-off-by: Logan Gunthorpe Signed-off-by: Stephen Bates --- default-configs/pc