Re: [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed

On Sat, Mar 29, 2025 at 10:03 AM LIU Zhiwei wrote: > > On 2025/3/14 03:30, Loïc Lefort wrote: > > Signed-off-by: Loïc Lefort > > Reviewed-by: Daniel Henrique Barboza > > --- > > target/riscv/pmp.c | 22 +++--- > > 1 file changed, 15 insert

Re: [PATCH v2 0/5] target/riscv: Smepmp fixes to match specification

Ping On Thu, Mar 13, 2025 at 8:30 PM Loïc Lefort wrote: > These patches fix Smepmp implementation to make it compliant with the spec. > > First patch limits RLB to CSR changes since RLB should not affect privilege > evaluation. Patch 2 extracts some common code into a function (to

[PATCH v2 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges

the correct behavior by removing mseccfg.RLB bypass from pmp_is_locked. RLB bypass when writing CSRs is implemented by adding a new pmp_is_readonly function that calls pmp_is_locked and check mseccfg.RLB. pmp_write_cfg and pmpaddr_csr_write are changed to use this new function. Signed-off-by: Loïc

[PATCH v2 0/5] target/riscv: Smepmp fixes to match specification

/ Loïc Lefort (5): target/riscv: pmp: don't allow RLB to bypass rule privileges target/riscv: pmp: move Smepmp operation conversion into a function target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode target/riscv: pmp: exit csr writes early if value was not changed t

[PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed

Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza --- target/riscv/pmp.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c5f6cdaccb..845915e0c8 100644 --- a/target/riscv/pmp.c +++ b/target

[PATCH v2 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked

Remove useless check in pmp_is_locked, the function will return 0 in either case. Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza --- target/riscv/pmp.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 845915e0c8..c685f7f2c5

[PATCH v2 3/5] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode

hese cases by using pmp_get_epmp_operation to convert between PMP configuration and Smepmp truth table cases. Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza --- target/riscv/pmp.c | 79 +- 1 file changed, 43 insertions(+), 36 delet

[PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function

Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza --- target/riscv/pmp.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e1e5ca589e..7d65dc24a5 100644 --- a/target/riscv/pmp.c +++ b/target

Re: [PATCH 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges

On Thu, Mar 13, 2025 at 12:40 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 2/25/25 1:00 PM, Loïc Lefort wrote: > > When Smepmp is supported, RLB allows bypassing locks when writing CSRs > but > > should not affect inte

Re: [PATCH 0/5] target/riscv: Smepmp fixes to match specification

On Tue, Feb 25, 2025 at 5:00 PM Loïc Lefort wrote: > Hi, > > These patches fix Smepmp implementation to make it compliant with the spec. > > First patch limits RLB to CSR changes since RLB should not affect privilege > evaluation. Patch 2 extracts some common code into a fu

[PATCH 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges

pmpaddr_csr_write are changed to use pmp_is_readonly while pmp_hart_has_privs keeps using pmp_is_locked. Signed-off-by: Loïc Lefort --- target/riscv/pmp.c | 43 --- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c

[PATCH 4/5] target/riscv: pmp: exit csr writes early if value was not changed

Signed-off-by: Loïc Lefort --- target/riscv/pmp.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e0ea436f8e..e4fee10d93 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -141,6 +141,11 @@ static

[PATCH 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked

Remove useless check in pmp_is_locked, the function will return 0 in either case. Signed-off-by: Loïc Lefort --- target/riscv/pmp.c | 5 - 1 file changed, 5 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index e4fee10d93..81c8bd71ce 100644 --- a/target/riscv/pmp.c +++ b

[PATCH 0/5] target/riscv: Smepmp fixes to match specification

order to match Smepmp specification. Patch 4 is a small optimization and last patch is just removing redundant code. Loïc Lefort (5): target/riscv: pmp: don't allow RLB to bypass rule privileges target/riscv: pmp: move Smepmp operation conversion into a function target/riscv: pmp: fix chec

[PATCH 3/5] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode

hese cases by using pmp_get_epmp_operation to convert between PMP configuration and Smepmp truth table cases. Signed-off-by: Loïc Lefort --- target/riscv/pmp.c | 81 -- 1 file changed, 43 insertions(+), 38 deletions(-) diff --git a/target/riscv/pmp.c b

[PATCH 2/5] target/riscv: pmp: move Smepmp operation conversion into a function

Signed-off-by: Loïc Lefort --- target/riscv/pmp.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ddb7e0d23c..b7f1430ff8 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -31,6 +31,15 @@ static

Re: [PATCH] Add epmp to extensions list and rename it to smepmp

On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan wrote: > > Smepmp is a ratified extension which qemu refers to as epmp. > Rename epmp to smepmp and add it to extension list so that > it is added to the isa string. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/cpu.c | 9 +

Re: [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.

Is there a reason to keep RISCV_EXCP_SEMIHOST handling separate from other exceptions? Otherwise it could be moved in the switch block just a few lines below. On Thu, May 18, 2023 at 1:39 PM Rajnesh Kanwal wrote: > RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local > interrupt as well