Hi,
> -Original Message-
> From: Li, Chunming
> Sent: Thursday, September 02, 2021 4:23 PM
> To: 'eric.au...@redhat.com'; chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei
> Subject: RE: [PATCH
Hi,
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Thursday, September 02, 2021 3:46 PM
> To: Li, Chunming; chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei
> Subject:
Hi,
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Wednesday, September 01, 2021 6:23 PM
> To: Li, Chunming; chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei
> Subject:
Hi,
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Wednesday, September 01, 2021 8:05 PM
> To: Li, Chunming; chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei
> Subject:
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:37 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATC
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:02 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re:
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:13 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATC
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:02 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re:
> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Thursday, August 26, 2021 11:57 PM
> To: Li, Chunming
> Cc: eric.au...@redhat.com; Liu, Renwei; qemu-...@nongnu.org; Wen,
> Jianxian; qemu-devel@nongnu.org
> Subject: Re: [PATCH] h
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Li, Chunming
---
hw/arm/smmuv3.c | 46
> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Friday, August 20, 2021 5:15 PM
> To: Li, Chunming
> Cc: eric.au...@redhat.com; qemu-...@nongnu.org; qemu-devel@nongnu.org;
> Wen, Jianxian; Liu, Renwei
> Subject: Re: [PATCH] hw/ar
. Add "smmuv3_sidmap" to set non PCI/PCIe devices SID value
. Pass non PCI/PCIe devices SID value to SMMU v3 model creation
. Store SMMU v3 device in virtual machine then non PCI/PCIe can get its
memory region later
Signed-off-by: Li, Chunming
---
hw/arm/virt.c
Replace "smmuv3_flush_config" with "g_hash_table_foreach_remove" based on
devices SID.
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
Signed-off-by: Li, Chunming
---
hw/arm/smmuv3.c | 35 ++---
Add PL330 DMA controller to test SMMU v3 connection and function.
The default SID for PL330 is 1 but we test other values, it works well.
Signed-off-by: Li, Chunming
---
hw/arm/virt.c | 92 ++-
include/hw/arm/virt.h | 1 +
2 files changed, 92
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Li, Chunming
---
hw/arm/smmuv3.c | 46
cannot configure its memory region manually.
So we update it and provide path.
The patch was reviewed and will be merged in target-arm.next for 6.2.
Li, Chunming (4):
hw/arm/smmuv3: Support non PCI/PCIe device connect with SMMU v3
hw/arm/smmuv3: Update implementation of CFGI commands based on
From: LCM
Add PL330 DMA controller to test SMMU v3 connection and function.
The default SID for PL330 is 1 but we test other values, it works well.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/virt.c | 92 ++-
include/hw/arm/v
From: LCM
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c
From: LCM
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
So we replace "smmuv3_flush_config" with "g_hash_table_foreach_remove" based on
devices SID.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c | 35 ++---
From: LCM
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c
. Add "smmuv3_sidmap" to set non PCI/PCIe devices SID value
. Pass non PCI/PCIe devices SID value to SMMU v3 model creation
. Store SMMU v3 device in virtual machine then non PCI/PCIe can get its
memory region later
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/virt.c
Add PL330 DMA controller to test SMMU v3 connection and function.
The default SID for PL330 is 1 but we test other values, it works well.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/virt.c | 92 ++-
include/hw/arm/virt.h | 1 +
. Add sid-map property to store non PCI/PCIe devices SID
. Create IOMMU memory regions for non PCI/PCIe devices based on their SID
. Update SID getting strategy for PCI/PCIe and non PCI/PCIe devices
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c | 46
"smmu_iommu_mr" function can't get MR according to SID for non PCI/PCIe devices.
So we replace "smmuv3_flush_config" with "g_hash_table_foreach_remove" based on
devices SID.
Signed-off-by: Chunming Li
Signed-off-by: Renwei Liu
---
hw/arm/smmuv3.c | 35 ++---
The current SMMU v3 model only support PCI/PCIe devices, so we update it for
non-PCI/PCIe devices.
. Add independent IOMMU memory regions for non-PCI/PCIe devices
. Add SID value property setting for non-PCI/PCIe devices
. Add PL330 DMA controller into "virt" machine and connect with SMMU v3
> On Fri, 20 Aug 2021 at 03:36, Li, Chunming
> wrote:
> >
> > The current SMMU V3 device model only support PCI/PCIe devices,
> > so we update it to support non-PCI/PCIe devices.
> >
> > hw/arm/smmuv3:
> > . Create IOMMU memory regions for
The current SMMU V3 device model only support PCI/PCIe devices,
so we update it to support non-PCI/PCIe devices.
hw/arm/smmuv3:
. Create IOMMU memory regions for non-PCI/PCIe devices based on their
SID
. Add sid-map property to store non-PCI/PCIe devices SID
. Update i
> On 8/20/21 4:36 AM, Li, Chunming wrote:
> > The current SMMU V3 device model only support PCI/PCIe devices,
> > so we update it to support non-PCI/PCIe devices.
> >
> > hw/arm/smmuv3:
> > . Create IOMMU memory regions for non-PCI/PCIe devices based
The current SMMU V3 device model only support PCI/PCIe devices,
so we update it to support non-PCI/PCIe devices.
hw/arm/smmuv3:
. Create IOMMU memory regions for non-PCI/PCIe devices based on their
SID
. Add sid-map property to store non-PCI/PCIe devices SID
. Update i
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