John Snow writes:
> On Mon, Oct 10, 2022 at 4:52 AM Lev Kujawski wrote:
>>
>> Always use the native CHS device parameters for the ATA commands READ
>> NATIVE MAX ADDRESS and READ NATIVE MAX ADDRESS EXT, not those limited
>> by the ATA command INITIALIZE_DEVICE_PARA
the command_disabled word to indicate
bits hardwired to 0.
* tests/qtest/libqos/pci.c: Verify that hardwired bits are actually
hardwired.
Signed-off-by: Lev Kujawski
---
tests/qtest/libqos/pci.c | 13 +++--
tests/qtest/libqos/pci.h | 1 +
2 files changed, 8 insertions(+), 6
Michael S. Tsirkin writes:
> On Sun, Sep 25, 2022 at 09:37:58AM +0000, Lev Kujawski wrote:
>> Devices like the PIIX3/4 IDE controller do not support certain modes
>> of operation, such as memory space accesses, and indicate this lack of
>> support by hardwiring the ap
e PIIX 3/4 IDE registers for hardwired bits (only what I
encountered testing proprietary firmware - PCICMD), and I do not have
access to my PIIX 3 system at the moment.
Kind regards,
Lev Kujawski
Lev Kujawski (2):
qpci_device_enable: Allow for command bits hardwired to 0
hw/ide/piix: Ignore wri
,
because the PIIX IDE controllers do not define their own state.
* tests/qtest/ide-test.c
Use the command_disabled field of the QPCIDevice testing model to
indicate that PCI_COMMAND_MEMORY is hardwired within PIIX 3/4 IDE
controllers.
Signed-off-by: Lev Kujawski
---
hw/core/machine.c
the prior behavior was that setting zero sectors
per track could lead to an FPE within ide_set_sector(). Thanks to
Alexander Bulekov for reporting this issue.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1243
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 21 +
1 fi
Verify that the ATA command READ NATIVE MAX ADDRESS returns the last
valid CHS tuple for the native device rather than any limit
established by INITIALIZE DEVICE PARAMETERS.
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-test.c | 47 +-
1 file changed
> On Tue, Sep 06, 2022 at 10:23:57AM -0400, Michael S. Tsirkin wrote:
> > On Thu, Jun 02, 2022 at 08:47:31PM +0000, Lev Kujawski wrote:
> > > ---
> > > This revised patch uses QEMU's built-in PCI bit-masking support rather
> > > than attempting to ma
the command_disabled word to indicate
bits hardwired to 0.
* tests/qtest/libqos/pci.c: Verify that hardwired bits are actually
hardwired.
Signed-off-by: Lev Kujawski
---
tests/qtest/libqos/pci.c | 13 +++--
tests/qtest/libqos/pci.h | 1 +
2 files changed, 8 insertions(+), 6
testing model to
indicate that PCI_COMMAND_MEMORY is hardwired in the PIIX3/4 IDE
controller.
Signed-off-by: Lev Kujawski
---
(v2) Use QEMU's built-in PCI bit-masking support rather than attempting
to manually filter writes. Thanks to Philippe Mathieu-Daude and
Michael S. Tsirki
Hi,
Thanks to everyone who contributed information to this report. As far as
issue #1 from David, I cannot reproduce the intermittent MS-DOS or
Windows NT 4 I/O failures with the latest git revision (a74c66b1). I am
similarly unable to reproduce Mdasoh's issue.
For the NT 4 testing script, I had
e translation (*ptrans) in the trace rather
than what was guessed.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/56
Buglink: https://bugs.launchpad.net/qemu/+bug/1745312
Signed-off-by: Lev Kujawski
---
hw/block/hd-geometry.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
di
PCI_COMMAND_MEMORY is hardwired in the PIIX3/4 IDE
controller.
Signed-off-by: Lev Kujawski
---
hw/ide/piix.c | 15 +++
tests/qtest/ide-test.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index de1f4f0efb..64620c5778 100644
--- a/hw/ide
geometry of the hard disk within the new field 'reset_reverts'.
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 29 ++---
include/hw/ide/internal.h | 3 +++
2 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
Verify correction of EXECUTE DEVICE DIAGNOSTIC introduced in commit
72423831c3 (hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE
DIAGNOSTIC, 2022-05-28).
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-test.c | 33 +
1 file changed, 33 insertions(+)
diff
ed to zero" for EXECUTE
DEVICE DIAGNOSTIC.
This deviation was uncovered by the ATACT Device Testing Program
written by Hale Landis.
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 7cbc0a54a7..b747191
the command_disabled word to indicate
bits hardwired to 0.
* tests/qtest/libqos/pci.c: Verify that hardwired bits are actually
hardwired.
Signed-off-by: Lev Kujawski
---
tests/qtest/libqos/pci.c | 13 +++--
tests/qtest/libqos/pci.h | 1 +
2 files changed, 8 insertions(+), 6
Change 'tmp_path' into an array of two members to accommodate another
disk image of size TEST_IMAGE_SIZE. This facilitates testing ATA
protocol aspects peculiar to secondary devices on the same controller.
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-t
Eliminate the remaining TODOs in hw/ide/piix.c by:
* Using pci_set_{size} functions to write the PIIX PCI configuration
space instead of manipulating it directly as an array; and
* Documenting the default register values by reference to the
controlling specification.
Signed-off-by: Lev
PC. Boston, MA: Addison-Wesley,
1997, p. 800-801.
Signed-off-by: Lev Kujawski
---
(v2) No functional changes. Add myself as the maintainer of this device,
per checkpatch; add technical details and references to commit log.
MAINTAINERS| 5 ++
hw/i386/Kconfig
and double word reads return a repeated sequence of the
written octet.
Reference platform:
TYAN S1686D (i440FX system board)
Signed-off-by: Lev Kujawski
---
(v2) First revision of test suite.
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
tests/qtest/postcard
ask before testing for it.
Signed-off-by: Lev Kujawski
---
(v4) Minor tweaks:
- Use spacing to delineate the functionality being tested.
- Ensure that PAM_WE is working by writing a mask within
that portion.
(v2-v3) No changes
tests/qtest/i440fx-test.c | 31 +
ory region
when writing to a read-only section marked for romd_mode.
Tested with SeaBIOS and AMIBIOS.
Signed-off-by: Lev Kujawski
---
(v4) Revamp to support execution in place for PCI ROMs in WE mode (2)
using the new romd memory section support in the QEMU MMU.
The romd memory secti
re.
Signed-off-by: Lev Kujawski
---
(v4) New patch.
tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 734 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tests/data/acpi/q35/SSDT.dimmpxm b/tests/data/acpi/q35/SSDT.dimmpxm
index
98e6f0e3f3bb02dd419e36bdd1
.
Kind regards,
Lev Kujawski
--- a/src/fw/shadow.c
+++ b/src/fw/shadow.c
@@ -28,7 +28,7 @@ union pamdata_u {
// Enable shadowing and copy bios.
static void
-__make_bios_writable_intel(u16 bdf, u32 pam0)
+make_bios_writable_intel(u16 bdf, u32 pam0)
{
// Read in current PAM settings from pci
CHS-based disk utilities and operating systems may adjust the logical
geometry of a hard drive to cope with the expectations or limitations
of software using the ATA INITIALIZE_DEVICE_PARAMETERS command.
Prior to this patch, INITIALIZE_DEVICE_PARAMETERS was a nop that
always returned success, rais
.
Signed-off-by: Lev Kujawski
---
tests/qtest/ide-test.c | 1 +
tests/qtest/libqos/pci.c | 13 +++--
tests/qtest/libqos/pci.h | 1 +
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/ide-test.c b/tests/qtest/ide-test.c
index 5bcb75a7e5..85a3967063 100644
--- a
S.
Signed-off-by: Lev Kujawski
---
(v3) Relocate ownership of the RAM address space into the respective
PAM chipsets. Eliminates the mtree duplicates.
Avoid changing the PAM region if possible.
Flush ROM after writing.
(v2) Write to an AddressSpace mapped over ram_memory instea
ew mask is written before switching
attributes;
- Switch back to PAM_RE after PAM_WE to read original contents;
- Tighten logic of the !WE write test because we know what the
original contents were; and
- Write the last mask before testing for it.
Signed-off-by: Lev Kujawski
---
(v3) No change.
(v2)
these systems (e.g., AMIBIOS) to track the state
of the boot process.
To aid firmware debugging, allow for tracing POST card values,
mimicking the [new value, old value] display format of actual cards.
Tested with AMIBIOS.
Signed-off-by: Lev Kujawski
---
hw/i386/Kconfig| 5 ++
hw
ew mask is written before switching
attributes;
- Switch back to PAM_RE after PAM_WE to read original contents;
- Tighten logic of the !WE write test because we know what the
original contents were; and
- Write the last mask before testing for it.
Signed-off-by: Lev Kujawski
---
(v2) No change.
t
ng an assert check.
- Remove the fourth PAM alias, for normal RAM-based reads and writes
of PAM regions, saving memory and clutter in mtree output.
Tested with SeaBIOS and AMIBIOS.
Signed-off-by: Lev Kujawski
---
(v2) Write to an AddressSpace mapped over ram_memory instead of using
a pointer,
ew mask is written before switching
attributes;
- Switch back to PAM_RE after PAM_WE to read original contents;
- Tighten logic of the !WE write test because we know what the
original contents were; and
- Write the last mask before testing for it.
Signed-off-by: Lev Kujawski
---
tests/qtest/i44
ng an assert check.
- Remove the fourth PAM alias, for normal RAM-based reads and writes
of PAM regions, saving memory and clutter in mtree output.
Tested with SeaBIOS and AMIBIOS.
Signed-off-by: Lev Kujawski
---
hw/pci-host/pam.c | 135 +++---
include/hw/pci
sectors are transferred. Up to a 50% increase
in PIO throughput can be achieved thanks to the reduction in system
call overhead and writing larger blocks (up to 128 KiB, with the size
limited by IDE_DMA_BUF_SECTORS).
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 62
. The attached patch improves
the rate by about 50% for me, and I would appreciate feedback on
whether this holds for others as well.
Kind regards,
Lev Kujawski
Lev Kujawski (1):
hw/ide/core: Accumulate PIO output within io_buffer prior to pwritev
hw/ide/core.c | 62
register would be left in an unspecified state without
this patch.
Signed-off-by: Lev Kujawski
---
This revised patch uses QEMU's built-in PCI bit-masking support rather
than attempting to manually filter writes. Thanks to Philippe Mathieu-
Daude and Michael S. Tsirkin for review and the pointer.
Eliminates the remaining TODOs in hw/ide/piix.c by:
- Using pci_set_{size} functions to write the PIIX PCI configuration
space instead of manipulating it directly as an array; and
- Documenting default register values by reference to the controlling
specification.
Signed-off-by: Lev Kujawski
register would be left in an unspecified state without
this patch.
Signed-off-by: Lev Kujawski
---
hw/ide/piix.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 76ea8fd9f6..f1d1168ecd 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
ed to zero" for EXECUTE
DEVICE DIAGNOSTIC.
This deviation was uncovered by the ATACT Device Testing Program
written by Hale Landis.
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index c2caa54285..5a24547
Signed-off-by: Lev Kujawski
---
hw/ide/atapi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ide/atapi.c b/hw/ide/atapi.c
index b626199e3d..88b2890faf 100644
--- a/hw/ide/atapi.c
+++ b/hw/ide/atapi.c
@@ -318,7 +318,7 @@ static void ide_atapi_cmd_reply(IDEState *s
Hello, I believe I have solved the underlying issue with the attached
patch. Verified against the behavior of an actual i440FX IDE controller.
See https://lists.nongnu.org/archive/html/qemu-
devel/2022-05/msg04229.html .
** Patch added:
"0001-ide_ioport_read-Return-lower-octet-of-data-register-.
y ATA device, such as an optical drive.
Resolves:
* [Bug 1639394] Unable to boot Solaris 8/9 x86 under Fedora 24
Signed-off-by: Lev Kujawski
---
hw/ide/core.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 3a5afff5d7..c2caa54285 100644
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