target/ppc: Improve Radix xlate level validation")
Reported-by: Victor Colombo
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
i
On 10/25/22 16:29, Daniel Henrique Barboza wrote:
On 10/21/22 14:01, Leandro Lupori wrote:
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be
: Leandro Lupori
Reviewed-by: Daniel Henrique Barboza
---
target/ppc/cpu.h | 4 +++-
target/ppc/helper_regs.c | 6 ++
target/ppc/translate.c | 4
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cca6c4e51c..28b9b8d4e3 100644
--- a
Changes from v1:
- Turn macro into an inline function
- Rename functions
Leandro Lupori (3):
accel/tcg: Add a quicker check for breakpoints
target/ppc: Add new PMC HFLAGS
target/ppc: Increment PMC5 with inline insns
accel/tcg/cpu-exec.c | 15
target/ppc/cpu.h | 4
to a reduction of
about 12% in Fedora's boot time.
Signed-off-by: Leandro Lupori
Reviewed-by: Daniel Henrique Barboza
---
target/ppc/helper.h | 1 +
target/ppc/power8-pmu.c | 74 +
target/ppc/power8-pmu.h | 3 ++
target/ppc/translate.c
s not
empty, it's possible to avoid the call overhead. An improvement of
about 3% in total time was measured on POWER9.
Signed-off-by: Leandro Lupori
---
accel/tcg/cpu-exec.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/
On 10/22/22 08:12, Richard Henderson wrote:
On 10/22/22 03:01, Leandro Lupori wrote:
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just
PMU tests from kernel selftests were run and all tests that pass on
master still pass with these changes.
Leandro Lupori (3):
accel/tcg: Add a quicker check for breakpoints
target/ppc: Add new PMC HFLAGS
target/ppc: Increment PMC5 with inline insns
accel/tcg/cpu-exec.c | 13 +++
: Leandro Lupori
---
target/ppc/cpu.h | 4 +++-
target/ppc/helper_regs.c | 6 ++
target/ppc/translate.c | 4
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cca6c4e51c..28b9b8d4e3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc
d the call overhead. An improvement of
about 3% in total time was measured on POWER9.
Signed-off-by: Leandro Lupori
---
accel/tcg/cpu-exec.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index f9e5cc9ba0..9eec01ad9a 10
to a reduction of
about 12% in Fedora's boot time.
Signed-off-by: Leandro Lupori
---
target/ppc/helper.h | 1 +
target/ppc/power8-pmu.c | 74 +
target/ppc/power8-pmu.h | 3 ++
target/ppc/translate.c | 28 ++--
4 files change
On 9/19/22 14:56, Leandro Lupori wrote:
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.
However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditio
to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Signed-off-by: Leandro Lupori
---
v3:
- make goto tb code 16-byte aligned
- code cleanup
v2: use stq to replace all instructions atomic
to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Signed-off-by: Leandro Lupori
---
v2: use stq to replace all instructions atomically
tcg/ppc/tcg-target.
On 9/8/22 18:44, Richard Henderson wrote:
On 9/8/22 22:18, Leandro Lupori wrote:
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.
However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit
to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Signed-off-by: Leandro Lupori
---
tcg/ppc/tcg-target.c.inc | 86 ++--
1 file changed, 73 inserti
On 7/14/22 15:45, Daniel Henrique Barboza wrote:
On 7/12/22 16:37, Leandro Lupori wrote:
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c | 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 64 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 87
Changes from v2:
- Moved TLBIE defines from helper.h to mmu-book3s-v3.h
Leandro Lupori (2):
target/ppc: Move tlbie[l] to decode tree
target/ppc: Implement ISA 3.00 tlbie[l]
target/ppc/cpu_init.c| 4 +-
target/ppc/helper.h | 2 +
target
On 6/28/22 10:39, Leandro Lupori wrote:
According to PowerISA 3.1B, Book III 6.7.6 programming note, the
page directory base addresses are expected to be aligned to their
size. Real hardware seems to rely on that and will access the
wrong address if they are misaligned. This results in a
On 6/24/22 16:50, Richard Henderson wrote:
On 6/24/22 12:14, Leandro Lupori wrote:
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation
Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 49 +++-
1 file changed, 38
to be properly
populated.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 705bff76be..00f2e9fa2e 100644
--- a/target/ppc/mmu
Check if partition and process tables are properly aligned, in
their size, according to PowerISA 3.1B, Book III 6.7.6 programming
note. Hardware and KVM also raise an exception in these cases.
Signed-off-by: Leandro Lupori
Reviewed-by: Fabiano Rosas
---
hw/ppc/spapr.c | 5
Changes from v2:
- Improved comments on patch 2
- Improved commit message on patch 3
- Now emulating CPU behavior on misaligned page table base addresses
Leandro Lupori (3):
ppc: Check partition and process table alignment
target/ppc: Improve Radix xlate level validation
target/ppc: Check
On 6/24/22 15:04, Richard Henderson wrote:
On 6/24/22 10:16, Leandro Lupori wrote:
Check if each page dir/table base address is properly aligned and
log a guest error if not, as real hardware behave incorrectly in
this case.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 15
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 64 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 87
Resent after rebasing and fixing conflicts with master.
Changes from v1:
- squashed first 2 commits into 1, because adding PPC_MEM_TLBIE to
P9/P10's insns_flags and moving only tlbie (and not tlbiel) to
decode tree breaks PowerPC64 instruction decoder initialization.
Leandro Lupo
Check if each page dir/table base address is properly aligned and
log a guest error if not, as real hardware behave incorrectly in
this case.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/ppc/mmu-radix64.c
Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 51 +++-
1 file changed, 40
Check if partition and process tables are properly aligned, in
their size, according to PowerISA 3.1B, Book III 6.7.6 programming
note. Hardware and KVM also raise an exception in these cases.
Signed-off-by: Leandro Lupori
---
hw/ppc/spapr.c | 5 +
hw/ppc/spapr_hcall.c
(). This also avoids calling it twice for
level 0, through ppc_radix64_walk_tree().
- Removed debug ifdefs from PDE/PTE alignment checks
Leandro Lupori (3):
ppc: Check partition and process table alignment
target/ppc: Improve Radix xlate level validation
target/ppc: Check page dir/table base
On 6/21/22 18:21, Fabiano Rosas wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
Leandro Lupori writes:
Check if the number and size
On 6/23/22 18:34, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 6/23/22 07:26, Leandro Lupori wrote:
On 6/21
On 6/21/22 18:26, Fabiano Rosas wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
Leandro Lupori writes:
Check if each page dir/table
On 6/21/22 08:05, Cédric Le Goater wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 6/20/22 22:27, Leandro Lupori wrote:
Check if
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:20, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:19, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:19, Lucas Coutinho wrote:
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
ned-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
On 6/15/22 16:19, Lucas Coutinho wrote:
From: Matheus Ferst
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Signed-off-by: Matheus Ferst
Signed-off-by: Lucas Coutinho
---
Reviewed-by: Leandro Lupori
Thanks,
Leandro
Changes from v1:
- squashed first 2 commits into 1, because adding PPC_MEM_TLBIE to
P9/P10's insns_flags and moving only tlbie (and not tlbiel) to
decode tree breaks PowerPC64 instruction decoder initialization.
Leandro Lupori (2):
target/ppc: Move tlbie[l] to decode tree
targe
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 64 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 87
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
Check if each page dir/table base address is properly aligned and
log a guest error if not, as real hardware behave incorrectly in
this case.
These checks are only performed when DEBUG_MMU is defined, to avoid
hurting the performance.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c
Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 36 +---
1 file changed, 29
Check if partition and process tables are properly aligned, in
their size, according to PowerISA 3.1B, Book III 6.7.6 programming
note. Hardware and KVM also raise an exception in these cases.
Signed-off-by: Leandro Lupori
---
hw/ppc/spapr.c | 5 +
hw/ppc/spapr_hcall.c
this part.
This patch series also improves the code that validates each Radix Tree
level, by checking the number of levels and the size of each one.
Finally, when DEBUG_MMU is defined, PDE/PTE base address alignment is
also checked and reported, to make it easier to detect invalid
configurations
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/insn32.decode | 1 +
target/ppc/translate.c | 22
target/ppc/translate/storage-ctrl-impl.c.inc | 16 +-
3 files changed, 12 insertions
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 7 ++
target/ppc/translate.c | 42 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 81
hard. In these cases, all
entries are flushed.
Resent after rebasing and fixing conflicts with master.
Leandro Lupori (3):
target/ppc: Move tlbie to decode tree
target/ppc: Move tlbiel to decode tree
target/ppc: Implement ISA 3.00 tlbie[l]
target/ppc/cpu_init.c| 4
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 7 ++
target/ppc/translate.c | 42 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 81
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/insn32.decode | 1 +
target/ppc/translate.c | 22
target/ppc/translate/storage-ctrl-impl.c.inc | 16 +-
3 files changed, 12 insertions
hard. In these cases, all
entries are flushed.
Leandro Lupori (3):
target/ppc: Move tlbie to decode tree
target/ppc: Move tlbiel to decode tree
target/ppc: Implement ISA 3.00 tlbie[l]
target/ppc/cpu_init.c| 4 +-
target/ppc/helper.h | 18
On 5/3/22 13:54, Cédric Le Goater wrote:
On 5/3/22 18:39, Leandro Lupori wrote:
Commit 74c4912f097bab98 changed check_tlb_flush() to use
tlb_flush_all_cpus_synced() instead of calling tlb_flush() on each
CPU. However, as side effect of this, a CPU executing a ptesync
after a tlbie will have
with
broadcast TLB flushes")
Signed-off-by: Leandro Lupori
---
target/ppc/helper_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 9a691d6833..1fa032e4d0 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/hel
On 4/20/22 15:18, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 4/20/22 10:54, Leandro Lupori wrote:
On 4/18
On 4/18/22 20:36, Richard Henderson wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 4/18/22 12:10, Leandro Lupori wrote:
+static
On 4/19/22 06:26, Peter Maydell wrote:
On Mon, 18 Apr 2022 at 20:15, Leandro Lupori
wrote:
Add semihosting support for PPC64. This implementation is
based on the standard for ARM semihosting version 2.0, as
implemented by QEMU and documented in
https://github.com/ARM-software/abi-aa
:
On 4/18/22 21:10, Leandro Lupori wrote:
Add support to build and run the multiarch hello test, that simply
prints a message and exits, through semihosting operations.
The linker script was imported from
https://github.com/legoater/pnv-test, that are the Microwatt tests
adapted to use a PowerNV
On 4/18/22 17:22, Cédric Le Goater wrote:
On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based on the standard for ARM semihosting version 2.0, as
implemented by QEMU and documented in
https://github.com/ARM-software/abi-aa/releases
The
On 4/20/22 15:05, Peter Maydell wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
On Mon, 18 Apr 2022 at 20:15, Leandro Lupori
wrote
On 4/18/22 17:22, Cédric Le Goater wrote:
diff --git a/semihosting/arm-compat-semi.c
b/semihosting/arm-compat-semi.c
index 7a51fd0737..e1279c316c 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -268,6 +268,31 @@ common_semi_sys_exit_extended(CPUState *cs, int n
, leaving the
task to the OS
(https://github.com/antonblanchard/microwatt/blob/master/mmu.vhdl#L402).
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/system/mmu-head.S | 142 ++
tests/tcg/ppc64/system/mmu.c | 764 ++
tests/tcg/ppc64/system/mmu.h | 9 +
3
Each Microwatt/PowerNV test use its own head.S file and thus needs
different build rules.
Also add rules to build and run all tests in LE mode.
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/Makefile.softmmu-rules | 34 +++
tests/tcg/ppc64/Makefile.softmmu-target | 121
PPC64 CPUs can change its endian dynamically, so semihosting code
must check its MSR at run time to determine if byte swapping is
needed.
Signed-off-by: Leandro Lupori
---
include/exec/softmmu-semi.h | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a
Operation Number Register: r3
Parameter Register: r4
Return Register: r3
Data block field size: 64 bits
Signed-off-by: Leandro Lupori
---
configs/devices/ppc64-softmmu/default.mak | 3 +++
qemu-options.hx | 18 -
semihosting/arm-compat-semi.c | 33
/head.S, also from pnv-test repo.
Signed-off-by: Leandro Lupori
---
MAINTAINERS | 2 +
tests/tcg/ppc64/Makefile.softmmu-target | 56 +
tests/tcg/ppc64/system/include/asm.h| 68
tests/tcg/ppc64/system/lib/boot.S | 84
Changes from v2:
- Added semihosting support for ppc64
- Use semihosting calls to exit tests, instead of using Processor
Attention instruction
- Use semihosting calls for console output, instead of programming
emulated serial hardware
Leandro Lupori (5):
ppc64: Add semihosting support
ppc64
On 3/31/22 12:47, Cédric Le Goater wrote:
Hello Leandro,
I think we should start looking at semihosting like Richard proposed
and for it, rework the QEMU attn implementation or may be use a special
form of scv.
It should not change too much the tests, only exit and output which
would remove th
Each Microwatt/PowerNV test use its own head.S file and thus needs
different build rules.
Also add rules to build and run all tests in LE mode.
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/Makefile.softmmu-rules | 34 +++
tests/tcg/ppc64/Makefile.softmmu-target | 119
, leaving the
task to the OS
(https://github.com/antonblanchard/microwatt/blob/master/mmu.vhdl#L402).
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/system/mmu-head.S | 142 ++
tests/tcg/ppc64/system/mmu.c | 764 ++
tests/tcg/ppc64/system/mmu.h | 9 +
3
made on top of these, mainly on boot.S,
that was based on pnv-test/mmu/head.S, to better integrate with
QEMU test infrastructure.
Signed-off-by: Leandro Lupori
---
MAINTAINERS | 2 +
tests/tcg/ppc64/Makefile.softmmu-target | 59
tests/tcg/ppc64/system
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: Leandro Lupori
---
hw/ppc/pnv_core.c | 6 ++
include/hw/ppc/pnv_core.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 19e8eb885f..eb59b44a6c 100644
--- a/hw/ppc
Goater (2):
target/ppc: Add support for the Processor Attention instruction
ppc/pnv: Activate support for the Processor Attention instruction
Leandro Lupori (3):
tests/tcg/ppc64: add basic softmmu test support
tests/tcg/ppc64: add MMU test sources
tests/tcg/ppc64: build PowerNV and LE tests
M
From: Cédric Le Goater
Check the HID0 bit to send signal, currently modeled as a checkstop.
The QEMU implementation adds an exit using the GPR[3] value (that's a
hack for tests)
Signed-off-by: Cédric Le Goater
Signed-off-by: Leandro Lupori
---
target/ppc/cpu.h | 8
t
On 3/25/22 06:50, Alex Bennée wrote:
Leandro Lupori writes:
On 24/03/2022 17:34, Alex Bennée wrote:
Leandro Lupori writes:
Adding a new, "virtual" TCG test target, ppc64le-softmmu, seems to
be the cleanest way to support both BE and LE tests for
ppc64-softmmu.
Signed-off-b
On 24/03/2022 17:34, Alex Bennée wrote:
Leandro Lupori writes:
Adding a new, "virtual" TCG test target, ppc64le-softmmu, seems to
be the cleanest way to support both BE and LE tests for
ppc64-softmmu.
Signed-off-by: Leandro Lupori
---
tests/Makefile.include
Each Microwatt/PowerNV test use its own head.S file and thus needs
different build rules.
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/Makefile.softmmu-target | 33 +++--
tests/tcg/ppc64/system/mmu-head.S | 1 +
2 files changed, 27 insertions(+), 7 deletions
Adding a new, "virtual" TCG test target, ppc64le-softmmu, seems to
be the cleanest way to support both BE and LE tests for
ppc64-softmmu.
Signed-off-by: Leandro Lupori
---
tests/Makefile.include| 7 ---
tests/tcg/configure.sh| 11
, leaving the
task to the OS
(https://github.com/antonblanchard/microwatt/blob/master/mmu.vhdl#L402).
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/system/mmu-head.S | 141 ++
tests/tcg/ppc64/system/mmu.c | 764 ++
tests/tcg/ppc64/system/mmu.h | 9 +
3
From: Cédric Le Goater
Signed-off-by: Cédric Le Goater
Signed-off-by: Leandro Lupori
---
hw/ppc/pnv_core.c | 6 ++
include/hw/ppc/pnv_core.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 19e8eb885f..eb59b44a6c 100644
--- a/hw/ppc
Goater (2):
target/ppc: Add support for the Processor Attention instruction
ppc/pnv: Activate support for the Processor Attention instruction
Leandro Lupori (4):
tests/tcg/ppc64: add basic softmmu test support
tests/tcg: add support for ppc64le softmmu tests
tests/tcg/ppc64: add MMU test sourc
made on top of these, mainly on boot.S,
that was based on pnv-test/mmu/head.S, to better integrate with
QEMU test infrastructure.
Signed-off-by: Leandro Lupori
---
tests/tcg/ppc64/Makefile.softmmu-target | 59
tests/tcg/ppc64/system/include/asm.h | 62
tests/tcg/ppc64
From: Cédric Le Goater
Check the HID0 bit to send signal, currently modeled as a checkstop.
The QEMU implementation adds an exit using the GPR[3] value (that's a
hack for tests)
Signed-off-by: Cédric Le Goater
Signed-off-by: Leandro Lupori
---
target/ppc/cpu.h | 8
t
ned-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 67c38f065b..5414fd63c1 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -204,7 +204,8 @@ s
On 01/12/2021 04:51, Cédric Le Goater wrote:
The ISO is too big for quick tests. Isn't there a minimum initrd ? can
we build a
builroot-like image for FreeBSD ?
FreeBSD doesn't use initrd. Its bootloader loads kernel modules directly
from disk (unfortunately, it doesn't work on PowerNV).
B
On 30/11/2021 05:44, Cédric Le Goater wrote:
It would be interesting to boot directly the PowerNV machine from a
FreeBSB kernel and a minimum inirtd without using the skiroot images
and an iso. Are images available ?
AFAIK there are no minimum initrd images available. The closest thing
would b
When updating the R bit of a PTE, the Hash64 MMU was using a wrong byte
offset, causing the first byte of the adjacent PTE to be corrupted.
This caused a panic when booting FreeBSD, using the Hash MMU.
Fixes: a2dd4e83e76b ("ppc/hash64: Rework R and C bit updates")
Signed-off-by: Lean
When updating the R bit of a PTE, the Hash64 MMU was using a wrong byte
offset, causing the first byte of the adjacent PTE to be corrupted.
This caused a panic when booting FreeBSD, using the Hash MMU.
Fixes: a2dd4e83e76b ("ppc/hash64: Rework R and C bit updates")
Signed-off-by: Lean
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