Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 15 +++
target/i386/tcg/sysemu/misc_helper.c | 7 +++
target/i386/tcg/sysemu/svm_helper.c | 15
Moved int_ctl into the CPUX86State structure to remove some
unnecessary stores and loads.
Signed-off-by: Lara Lazier
---
slirp| 2 +-
target/i386/cpu.c| 2 +-
target/i386/cpu.h| 1 +
target/i386/machine.c
Patch 2 adds VGIF capability to mask virtual interrupts.
Patches 3 and 4 fix bugs related to vTPR, while patch 1 refactors
int_ctl into the state structure to simplify the fixes in the
following patches.
Lara Lazier (4):
target/i386: Moved int_ctl into CPUX86State structure
target/i386: Added
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier
---
target/i386/cpu.c | 7 +--
target/i386/cpu.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 12
3 files changed, 19 insertions
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/tcg/sysemu/svm_helper.c
b/target/i386/tcg/sysemu
Moved int_ctl into the CPUX86State structure to remove some
unnecessary stores and loads.
Signed-off-by: Lara Lazier
---
slirp| 2 +-
target/i386/cpu.c| 2 +-
target/i386/cpu.h| 1 +
target/i386/machine.c
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/tcg/sysemu/svm_helper.c
b/target/i386/tcg/sysemu
Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 15 +++
target/i386/tcg/sysemu/misc_helper.c | 7 +++
target/i386/tcg/sysemu/svm_helper.c | 15
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode
without
causing a VMEXIT. (APM2 15.33.1)
This is currently untested; I sent it out as part of my GSoC project.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 2 ++
target/i386/svm.h
Patch 2 adds VGIF capability to mask virtual interrupts.
Patches 3 and 4 fix bugs related to vTPR, while patch 1 refactors
int_ctl into the state structure to simplify the fixes in the
following patches.
Lara Lazier (4):
target/i386: Moved int_ctl into CPUX86State structure
target/i386: Added
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier
---
target/i386/cpu.c | 7 +--
target/i386/cpu.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 12
3 files changed, 19 insertions
~0UL has 64 bits on Linux and 32 bits on Windows.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/512";.
Reported-by: Volker Rümelin
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 2 +-
target/i386/tcg/sysemu/svm_helper.c | 2 +-
2 files changed, 2 insertions(
APM2 requires that VMRUN and VMLOAD canonicalize (sign extend to 63
from 48/57) all base addresses in the segment registers that have been
respectively loaded.
Signed-off-by: Lara Lazier
---
target/i386/cpu.c | 19 +++
target/i386/cpu.h | 2
t 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier
---
target/i386/cpu.c | 3 ++-
target/i386/svm.h | 6 ++
target/i386/tcg/sysemu/svm_helper.c | 31 +++--
3 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/i
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier
v1->v2: Fixed Mask
The APM2 states that The processor takes a virtual INTR interrupt
if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending
whose priority is greater than the value in V_TPR.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c |
VMRUN exits with SVM_EXIT_ERR if either:
* The event injected has a reserved type.
* When the event injected is of type 3 (exception), and the vector that
has been specified does not correspond to an exception.
This does not fix the entire exc_inj test in kvm-unit-tests.
Signed-off-by: Lara
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier
All MBZ in CR3 must be zero (APM2 15.5)
Added checks in both helper_vmrun and helper_write_crN.
When EFER.LMA is zero the upper 32 bits needs to be zeroed.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 7 +++
target/i386/tcg/sysemu/svm_helper.c | 10 +++---
2
.PAE, CS.L and CS.D
are all invalid.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 5
target/i386/tcg/sysemu/svm_helper.c | 40 +
2 files changed, 45 insertions(+)
diff --git a/target
All MBZ bits in CR4 must be zero. (APM2 15.5)
Added reserved bitmask and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 31
target/i386/tcg/sysemu/misc_helper.c | 3 +++
target/i386/tcg
The APM2 states that The processor takes a virtual INTR interrupt
if V_IRQ and V_INTR_PRIO indicate that there is a virtual interrupt pending
whose priority is greater than the value in V_TPR.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 12 +++-
1 file changed
-zero EFER.LME, CR0.PG, CR4.PAE, CS.L and CS.D
are all invalid.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 39 +
2 files changed, 41 inser
DR6[63:32] and DR7[63:32] are reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/svm.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 8 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff
All MBZ bits in CR3 and CR4 must be zero. (APM2 15.5)
Added reserved bitmask for CR4 and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 29
target/i386/tcg/sysemu/misc_helper.c | 6
address: 438fff
Lara Lazier (4):
target/i386: Added MSRPM and IOPM size check
target/i386: Added DR6 and DR7 consistency checks
target/i386: Added consistency checks for EFER
target/i386: Added VMRUN consistency checks for CR3 and CR4
target/i386/cpu.h| 31
The address of the last entry in the MSRPM and
in the IOPM must be smaller than the largest physical address.
(APM2 15.10-15.11)
Signed-off-by: Lara Lazier
---
target/i386/svm.h | 3 +++
target/i386/tcg/sysemu/svm_helper.c | 15 +++
2 files changed, 18 insertions
Zero VMRUN intercept and ASID should cause an immediate VMEXIT
during the consistency checks performed by VMRUN.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/svm_helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --
The combination of unset CD and set NW bit in CR0 is illegal.
CR0[63:32] are also reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 2 ++
target/i386/svm.h | 2 ++
target
When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.
Signed-off-by: Lara Lazier
---
target/i386/tcg/sysemu/misc_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target
Added cpu_svm_has_intercept to reduce duplication when checking the
corresponding intercept bit outside of cpu_svm_check_intercept_param
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 3 +
target/i386/tcg/sysemu/svm_helper.c | 105 +++-
2 files
63:32: 180010011
* CR0 63:32: 1080010011
* CR0 63:32: 10080010011
* CR0 63:32: 100080010011
v1->v2: introduced cpu_svm_has_intercept to avoid defining bitmasks for
intercepts
Lara Lazier (4):
target/i386: Refactored intercept checks into cpu_svm_has_interc
The combination of unset CD and set NW bit in CR0 is illegal.
CR0[63:32] are also reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/cpu.h | 2 ++
target/i386/svm.h | 1 +
target
Zero VMRUN intercept and ASID should cause an immediate VMEXIT
during the consistency checks performed by VMRUN.
(AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier
---
target/i386/svm.h | 2 ++
target/i386/tcg/sysemu/svm_helper.c | 10
When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.
Signed-off-by: Lara Lazier
---
target/i386/cpu.h| 2 ++
target/i386/tcg/sysemu/misc_helper.c | 9 +
2 files changed, 11 insertions(+)
diff --git a
63:32: 180010011
* CR0 63:32: 1080010011
* CR0 63:32: 10080010011
* CR0 63:32: 100080010011
Lara Lazier (3):
target/i386: Added consistency checks for VMRUN intercept and ASID
target/i386: Added consistency checks for CR0
target/i386: Added Intercept CR0 writes check
Hi everyone!
My name is Lara, and I am one of this year's GSoC students. I am studying
computer science in Zürich, and I will start my master's in September. For
my GSoC project, I am working with Paolo Bonzini on fixing and extending
the SVM implementation in QEMU.
I am very excited to learn man
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