; advanced users can enable/disable register
groups as required.
Signed-off-by: Konrad Schwarz
---
target/riscv/cpu.c | 327 +
1 file changed, 303 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..eb9
uest's 2nd level paging tables similarly to the
existing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual'
feature of RISC-V target descriptions.
This patch adds the `v' (hypervisor virtualization mode) bit
to `priv' as specified by section 4.9.1 of version 1.0 of the
RISC-V Debug Support specification.
Signed-off-by: Konra
set of the RISC-V Control and Status Registers (CSRs).
Signed-off-by: Konrad Schwarz
---
target/riscv/csr.c| 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++
target/riscv/csr64-op-gdbserver.h | 76 +++
target/riscv/gdb_csr_type_group.c | 16 ++
ta
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +-
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69
ing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
Konrad Schwarz (5):
RISC-V: larger and more consiste
set of the RISC-V Control and Status Registers (CSRs).
Signed-off-by: Konrad Schwarz
---
target/riscv/csr.c| 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++
target/riscv/csr64-op-gdbserver.h | 76 +++
target/riscv/gdb_csr_types.c
This is analog to the existing 'info mem' command and is implemented
using the same machinery.
Signed-off-by: Konrad Schwarz
---
hmp-commands-info.hx | 16 +
include/monitor/hmp-target.h | 2 +
target/riscv/monitor.c | 135 +-
Enable the print (p) command to display both
general-purpose and Contral and Status (CSR) registers.
General purpose registers can be named using the xN form
or their ABI names (zero, ra, sp, a0, s1, t2).
Signed-off-by: Konrad Schwarz
---
target/riscv/monitor.c | 69
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual'
feature of RISC-V target descriptions.
This patch adds the `v' (hypervisor virtualization mode) bit
to `priv' as specified by section 4.9.1 of version 1.0 of the
RISC-V Debug Support specification.
Signed-off-by: Konra
; advanced users can enable/disable register
groups as required.
Signed-off-by: Konrad Schwarz
---
target/riscv/cpu.c | 327 +
1 file changed, 303 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..eb9
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