[PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers'

2022-01-04 Thread Konrad Schwarz
; advanced users can enable/disable register groups as required. Signed-off-by: Konrad Schwarz --- target/riscv/cpu.c | 327 + 1 file changed, 303 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..eb9

[PATCH v2 0/5] Improve RISC-V debugging support.

2022-01-04 Thread Konrad Schwarz
uest's 2nd level paging tables similarly to the existing `info mem' command. 4) Improve QEMU RISC-V target descriptions for GDB. In particular, add type information for many control and status registers. 5) Extend the virtual `priv' register with hypervisor virtualization status.

[PATCH v2 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register

2022-01-04 Thread Konrad Schwarz
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual' feature of RISC-V target descriptions. This patch adds the `v' (hypervisor virtualization mode) bit to `priv' as specified by section 4.9.1 of version 1.0 of the RISC-V Debug Support specification. Signed-off-by: Konra

[PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver

2022-01-04 Thread Konrad Schwarz
set of the RISC-V Control and Status Registers (CSRs). Signed-off-by: Konrad Schwarz --- target/riscv/csr.c| 2 + target/riscv/csr32-op-gdbserver.h | 109 ++ target/riscv/csr64-op-gdbserver.h | 76 +++ target/riscv/gdb_csr_type_group.c | 16 ++ ta

[PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations

2022-01-04 Thread Konrad Schwarz
This is analog to the existing 'info mem' command and is implemented using the same machinery. Signed-off-by: Konrad Schwarz --- hmp-commands-info.hx | 16 + include/monitor/hmp-target.h | 2 + target/riscv/monitor.c | 135 +-

[PATCH v2 2/5] RISC-V: monitor's print register functionality

2022-01-04 Thread Konrad Schwarz
Enable the print (p) command to display both general-purpose and Contral and Status (CSR) registers. General purpose registers can be named using the xN form or their ABI names (zero, ra, sp, a0, s1, t2). Signed-off-by: Konrad Schwarz --- target/riscv/monitor.c | 69

[PATCH v1 0/5] Improve RISC-V debugging support.

2022-01-02 Thread Konrad Schwarz
ing `info mem' command. 4) Improve QEMU RISC-V target descriptions for GDB. In particular, add type information for many control and status registers. 5) Extend the virtual `priv' register with hypervisor virtualization status. Konrad Schwarz (5): RISC-V: larger and more consiste

[PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver

2022-01-02 Thread Konrad Schwarz
set of the RISC-V Control and Status Registers (CSRs). Signed-off-by: Konrad Schwarz --- target/riscv/csr.c| 2 + target/riscv/csr32-op-gdbserver.h | 109 ++ target/riscv/csr64-op-gdbserver.h | 76 +++ target/riscv/gdb_csr_types.c

[PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations

2022-01-02 Thread Konrad Schwarz
This is analog to the existing 'info mem' command and is implemented using the same machinery. Signed-off-by: Konrad Schwarz --- hmp-commands-info.hx | 16 + include/monitor/hmp-target.h | 2 + target/riscv/monitor.c | 135 +-

[PATCH v1 2/5] RISC-V: monitor's print register functionality

2022-01-02 Thread Konrad Schwarz
Enable the print (p) command to display both general-purpose and Contral and Status (CSR) registers. General purpose registers can be named using the xN form or their ABI names (zero, ra, sp, a0, s1, t2). Signed-off-by: Konrad Schwarz --- target/riscv/monitor.c | 69

[PATCH v1 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register

2022-01-02 Thread Konrad Schwarz
esents virtual debug registers in the `org.gnu.gdb.riscv.virtual' feature of RISC-V target descriptions. This patch adds the `v' (hypervisor virtualization mode) bit to `priv' as specified by section 4.9.1 of version 1.0 of the RISC-V Debug Support specification. Signed-off-by: Konra

[PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers'

2022-01-02 Thread Konrad Schwarz
; advanced users can enable/disable register groups as required. Signed-off-by: Konrad Schwarz --- target/riscv/cpu.c | 327 + 1 file changed, 303 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..eb9