[1/1] tcg/mips: Fix SoftTLB comparison on mips backend

rate increase from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform). Signed-off-by: Kele Huang Signed-off-by: Fuxin Zhang Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg

[1/1] tcg/mips: Fix SoftTLB comparison on mips backend

rate increase from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform). Signed-off-by: Kele Huang --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8738a3a581..8b16726242 100644 --- a

Re: [PATCH v3 1/1] accel/tcg: Fix computing of is_write for MIPS

> +case 015: /* SDXC1 */ I just found a comment mistake about SUXC1, and I have rectified it and resent a new patch. On Tue, 29 Sep 2020 at 09:59, Kele Huang wrote: > Thank you so much! > > > On Mon, 28 Sep 2020 at 16:14, Aleksandar Markovic < > aleksandar.qemu.d

[PATCH v5 1/1] accel/tcg: Fix computing of is_write for MIPS

Detect all MIPS store instructions in cpu_signal_handler for all available MIPS versions, and set is_write if encountering such store instructions. This fixed the error while dealing with self-modified code for MIPS. Reviewed-by: Richard Henderson Signed-off-by: Kele Huang Signed-off-by: Xu

Re: [PATCH v3 1/1] accel/tcg: Fix computing of is_write for MIPS

Thank you so much! On Mon, 28 Sep 2020 at 16:14, Aleksandar Markovic < aleksandar.qemu.de...@gmail.com> wrote: > > > On Sunday, September 27, 2020, Kele Huang wrote: > >> Sorry about that, I only got maintainers by './scripts/get_maintainer.pl >> -f acc

Re: [PATCH v4 1/1] accel/tcg: Fix computing of is_write for MIPS

e Mathieu-Daudé wrote: > On 9/27/20 10:20 AM, Kele Huang wrote: > > Detect all MIPS store instructions in cpu_signal_handler for all > available > > MIPS versions, and set is_write if encountering such store instructions. > > > > This fixed the error while dealing with sel

[PATCH v4 1/1] accel/tcg: Fix computing of is_write for MIPS

Detect all MIPS store instructions in cpu_signal_handler for all available MIPS versions, and set is_write if encountering such store instructions. This fixed the error while dealing with self-modified code for MIPS. Reviewed-by: Richard Henderson Signed-off-by: Kele Huang Signed-off-by: Xu

Re: [PATCH v3 1/1] accel/tcg: Fix computing of is_write for MIPS

Fixed! I have resent a v4 patch which contains SUXC1. Thank you! On Fri, 25 Sep 2020 at 22:58, Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/25/20 1:33 AM, Kele Huang wrote: > > Detect all MIPS store instructions in cpu_signal_handler for all > available >

Re: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

Got it. Thank you again! I have resend a brand new v3 patch. On Thu, 24 Sep 2020 at 22:05, Richard Henderson < richard.hender...@linaro.org> wrote: > On 9/23/20 2:38 AM, Kele Huang wrote: > > Detect mips store instructions in cpu_signal_handler for all MIPS > > versions

[PATCH v3 1/1] accel/tcg: Fix computing of is_write for MIPS

Detect all MIPS store instructions in cpu_signal_handler for all available MIPS versions, and set is_write if encountering such store instructions. This fixed the error while dealing with self-modified code for MIPS. Signed-off-by: Kele Huang Signed-off-by: Xu Zou --- accel/tcg/user-exec.c

Re: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

Richard who made a comment in v1. > > On 9/23/20 11:38 AM, Kele Huang wrote: > > Detect mips store instructions in cpu_signal_handler for all MIPS > > versions, and set is_write if encountering such store instructions. > > > > This fixed the error while dealing with self

Re: [PATCH 1/1] accel/tcg: Fix computing is_write for mips

dealing with self-modified code for MIPS. Signed-off-by: Kele Huang Signed-off-by: Xu Zou --- accel/tcg/user-exec.c | 51 ++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bb039eb32d

Re: [PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

Got it. Thank you very much! I will resend the same v2 patch to v1 thread. On Wed, 23 Sep 2020 at 19:08, Philippe Mathieu-Daudé wrote: > Cc'ing the TCG MIPS maintainers, and also > Cc'ing Richard who made a comment in v1. > > On 9/23/20 11:38 AM, Kele Huang wrote:

[PATCH v2 1/1] accel/tcg: Fix computing of is_write for mips

Detect mips store instructions in cpu_signal_handler for all MIPS versions, and set is_write if encountering such store instructions. This fixed the error while dealing with self-modifed code for MIPS. Signed-off-by: Kele Huang Signed-off-by: Xu Zou --- accel/tcg/user-exec.c | 51

[PATCH 1/1] accel/tcg: Fix computing is_write for mips

Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since MIPS64r1, and MIPS32 since MIPS32r2. Signed-off-by: Kele Huang --- accel/tcg/user-exec.c | 21 + 1 file changed, 21 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bb039eb32d

[PATCH 0/1] accel/tcg: Fix computing is_write for mips

Detect mips store instructions SWXC1 and SDXC1 for MIPS64 since MIPS64r1, and MIPS32 since MIPS32r2. Can work better with self-modifying codes (SMC) now. Kele Huang (1): accel/tcg: Fix computing is_write for mips accel/tcg/user-exec.c | 21 + 1 file changed, 21 insertions