From: Peter Maydell
Date: Fri, 07 Mar 2025 13:26:14 +
> Unless there's a strong reason for doing something different,
> I would favour following the same pattern arm does for this.
Thanks for the suggested cleanup; this looks a lot nicer now.
From 02d0f2b006500dec62e91bd571a8722c354133e5 Mo
> Ths code does what it intends to, and I'm not saying we should
> definitely *not* have it. I do think it's worth considering whether
> we need it, given that you can already load an ELF image via the
> generic loader (-device loader).
Also sorry for not getting back to this; we've been busy wit
The documentation says the vector is at 0xff80, instead of the
previous value of 0xffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.
Signed-off-by: Keith Packard
---
target/rx/helper.c | 2 +-
1 file changed,
The existing loader supports raw binary blobs with the entry point
defined as the start of the blob. Add support for loading ELF files by
first checking if the provided filename has a valid ELF header,
falling back to the existing loader code when that fails.
Signed-off-by: Keith Packard
---
hw/
With feedback from Peter Maydell and Richard Henderson, I've updated
this series to address two concerns:
1. The hardware model is now responsible for guiding the CPU reset
process.
2. Loading the reset vector from memory is now delayed until cpu_reset
is finished to ensure memory_dispa
Functions which modify virtual machine state (such as virtual
registers stored in memory) must not be marked TCG_CALL_NO_WG as that
tells the optimizer that virtual registers values already loaded in
machine registers are still valid, hence discards any changes which
these helpers may have made. Th
This ensure that the CPU gets reset every time QEMU resets. Use either
the kernel entry point or the reset vector if no kernel was loaded.
Signed-off-by: Keith Packard
---
hw/rx/rx-gdbsim.c | 36 +++-
target/rx/cpu.c | 9 ++---
target/rx/cpu.h | 3 +++
3
> > By delaying the load of the reset vector to the reset_exit phase,
> > you can always load from rom.
> I'm not sure how -- the ROM image is discarded when it gets loaded into
> read-only memory. If loaded to read-write memory, I bet it would
> stay around.
Ah, but by delaying until after cpu_
> So I'm OK with this patch doing this the way it does,
> except that I have one question: what's that
> process_queued_cpu_work() call doing? We don't need
> that on the Arm equivalent...
Yup, I needed that because I was running this bit at cpu_reset_hold
time, not waiting until after cpu reset
From: Richard Henderson
Date: Sat, 15 Feb 2025 10:24:05 -0800
> By delaying the load of the reset vector to the reset_exit phase,
> you can always load from rom.
I'm not sure how -- the ROM image is discarded when it gets loaded into
read-only memory. If loaded to read-write memory, I bet it wou
From: Peter Maydell
Date: Mon, 17 Feb 2025 09:53:58 +
> Reset of devices not plugged into buses (of which CPUs
> are the most common kind) is a mess. But having them
> call qemu_register_reset() themselves in their own
> realize method isn't the usual workaround. Instead we
> get the board co
> Functions which modify virtual machine state (such as virtual
> registers stored in memory) must not be marked TCG_CALL_NO_WG as that
> tells the optimizer that virtual registers values already loaded in
> machine registers are still valid, hence discards any changes which
> these helpers may ha
The documentation says the vector is at 0xff80, instead of the
previous value of 0xffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.
Signed-off-by: Keith Packard
---
target/rx/helper.c | 2 +-
1 file changed,
The ROM images all get deleted as they've been loaded to memory, so we
can't go fetch the reset vector from there. Instead, fetch it from
memory. To make that work, we need to execute the delayed mmu setup
function tcg_commit_cpu as that wires up memory dispatching.
Signed-off-by: Keith Packard
-
Users can use -device loader to get an ELF file loaded to
memory, so we don't need to require one of these options.
Signed-off-by: Keith Packard
---
hw/rx/rx-gdbsim.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c
index 88c8f12c10..4afd77efd5 100644
-
I'm getting a Renesas toolchain working and found a couple of bugs
and a few fixes in the qemu target code for this device.
The two critical bugs which are fixed:
1. Exception vector base address is incorrect. The
right value is 0xff80.
2. A bunch of opcode helper functions are incorre
Functions which modify virtual machine state (such as virtual
registers stored in memory) must not be marked TCG_CALL_NO_WG as that
tells the optimizer that virtual registers values already loaded in
machine registers are still valid, hence discards any changes which
these helpers may have made.
S
This ensure that the CPU gets reset every time QEMU resets.
Signed-off-by: Keith Packard
---
target/rx/cpu.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 37a6fdd569..04dd34b310 100644
--- a/target/rx/cpu.c
+++ b/target/rx
> When I developped the FPU emulation I compared the result of QEMU and a real
> hardware using
> https://github.com/vivier/m68k-testfloat and
> https://github.com/vivier/m68k-softfloat
It looks like the second of those has similar issues with m68k denorms?
https://github.com/vivier/m68k-soft
> That does look like a correct change. I'll fold it in.
> Please let us know if you encounter anything else.
Thanks so much. With these fixes, all of my long double math library
tests in picolibc are passing now (once I fixed a bunch of additional
m68k-denorm related math library bugs). That in
> Motorola treats denormals with explicit integer bit set as
> having unbiased exponent 0, unlike Intel which treats it as
> having unbiased exponent 1 (like all other IEEE formats).
Thanks for having a look at this. Your patch fixes a couple of cases,
but there are further adventures that await
I'm doing some testing of an fmal implementation and discovered some
"odd" results on m68k where the emulated 80-bit FPU is generating
results that don't match how GCC computes things. Assuming gcc is
correct, this means there are some subtle bugs in how qemu is handling
denorms for this platform.
Add helpers for reading/writing the 68881 FPSR register so that
changes in floating point exception state can be seen by the
application.
Call these helpers in pre_load/post_load hooks to synchronize
exception state.
Signed-off-by: Keith Packard
---
target/m68k/cpu.c| 12 +++
target
> Good catch. Mostly ok.
Thanks much for looking at this.
> No need for inline markers.
Thanks.
> In general it is bad form to call HELPER(foo) directly. In this case
> it doesn't hurt, but better form to reverse the implementations.
Good point. I had copied this from the arm vfp code which
Add helpers for reading/writing the 68881 FPSR register so that
changes in floating point exception state can be seen by the
application.
Signed-off-by: Keith Packard
---
target/m68k/cpu.h| 2 ++
target/m68k/fpu_helper.c | 72
target/m68k/helper.
The first two patches mirror similar patches I recently sent for nios2.
1. Use correct parameter for EXIT (d1 instead of d0)
2. Fix use of deposit64 in LSEEK (argument order was incorrect)
The second patch has also been submitted by Peter Maydell, it's
included here because it was required to g
Instead of using d0 (the semihost function number), use d1 (the
provide exit status).
Signed-off-by: Keith Packard
---
target/m68k/m68k-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
index 88ad9ba814..12235759c7 10
According to the m68k semihosting spec:
"The instruction used to trigger a semihosting request depends on the
m68k processor variant. On ColdFire, "halt" is used; on other processors
(which don't implement "halt"), "bkpt #0" may be used."
Add support for non-CodeFire processors by matching BKP
The arguments for deposit64 are (value, start, length, fieldval); this
appears to have thought they were (value, fieldval, start,
length). Reorder the parameters to match the actual function.
Signed-off-by: Keith Packard
---
target/m68k/m68k-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
> Yeah, the closest to a "standard" we have for nios2 is that
> I asked the Codesourcery folks to document it in the libgloss
> sources and put the URL to it in a comment at the top of
> nios2-semi.c, given that there's no official spec and the
> original and main guest-side user is libgloss.
> m6
Instead of using R_ARG0 (the semihost function number), use R_ARG1
(the provided exit status).
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index 3738774976
> says that for HOSTED_EXIT the exit code is in r5,
> not in a parameter block pointed to by r5. That
> would imply that the correct change is to use
> R_ARG1 rather than R_ARG0 here.
Ah, thanks -- I hadn't managed to find the actual standard yet. I'll
resubmit with that fixed.
--
-keith
sign
The arguments for deposit64 are (value, start, length, fieldval); this
appears to have thought they were (value, fieldval, start,
length). Reorder the parameters to match the actual function.
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 del
Instead of using the function number (which is always zero), fetch the
application-provided exit code argument and pass that to the two exit
functions.
Signed-off-by: Keith Packard
---
target/nios2/nios2-semi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/nios2
'lock_user' allocates a host buffer to shadow a target buffer,
'unlock_user' copies that host buffer back to the target and frees the
host memory. If the completion function uses the target buffer, it
must be called after unlock_user to ensure the data are present.
This caused the arm-compatible T
Richard Henderson writes:
> Reported-by: Keith Packard
> Signed-off-by: Richard Henderson
Looks good to me, and it passes my very simple test when run on s390.
Tested-by: Keith Packard
--
-keith
signature.asc
Description: PGP signature
Richard Henderson writes:
> The signed information is still there, merged with the typecode:
>
> #define dh_typecode_void 0
> #define dh_typecode_noreturn 0
> #define dh_typecode_i32 2
> #define dh_typecode_s32 3
> #define dh_typecode_i64 4
> #define dh_typecode_s64 5
> #define dh_typecode_ptr 6
Commit 7319d83a (tcg: Combine dh_is_64bit and dh_is_signed to
dh_typecode) converted the tcg type system to a 3-bit field from two
separate 1-bit fields. This subtly lost the 'signed' information from
the types as it uses the dh_alias macro to reduce the types down to
basic machine types. However,
Alex Bennée writes:
> +asprintf(&heap_info, "heap: %p -> %p\n", info.heap_base,
> info.heap_limit);
> +__semi_call(SYS_WRITE0, (uintptr_t) heap_info);
> +if (info.heap_base != brk) {
That requires qemu to know a lot about the run-time environment, which
it rarely does in my experien
Alex Bennée writes:
> Note: we aren't currently testing riscv32 due to missing toolchain for
> check-tcg tests.
That's surprising -- the usual risc-v toolchain supports both 64- and
32- bit targets.
Othewise, this patch is
Reviewed-by: Keith Packard
--
-keith
signature.asc
Description: PG
Alistair Francis writes:
> I have started on the effort, but I have not finished yet. Adding
> riscv_cpu_is_32bit() was the first step there and I have some more
> patches locally but I don't have anything working yet.
That's awesome. I think waiting until we see what APIs you're developing
for
Peter Maydell writes:
> ILP32 for AArch64 is a zombie target -- it is kinda-sorta
> supported in some toolchains but has no support in eg
> the Linux syscall ABI. The semihosting ABI does not implement
> any kind of ILP32 variant -- you can have A32/T32 (AArch32)
> semihosting, where register and
Peter Maydell writes:
> For semihosting for Arm what matters is "what state is the core
> in at the point where it makes the semihosting SVC/HLT/etc insn?".
Ok, that means we *aren't* talking about -mabi=ilp32, which is good --
in my current picolibc implementation, the semihosting code uses a p
Peter Maydell writes:
> Also, you don't seem to have the correct "is the CPU in
> 32-bit or 64-bit mode" test here: you cannot rely on target_ulong
> being the right size, you must make a runtime check.
Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode,
or whether an aarch64
Alex Bennée writes:
> I'm not sure this every worked properly and it's certainly not
> exercised by check-tcg or Peter's semihosting tests. Hoist it into
> it's own helper function and attempt to validate the results in the
> linux-user semihosting test at the least.
The patch is mostly code mot
When checking whether there is a live gdb connection, code shouldn't
use 'gdbserver_state.init' as that value is set when the
gdbserver_state structure is initialized in init_gdbserver_state, not
when the gdb socket has a valid connection.
I've created two new functions to manage the gdb connectio
Alex Bennée writes:
> It would be better to wrap the test in a function (static bool
> is_connected()?) so the semantic meaning is clear in the code and we can
> fix things in one place if needed.
That makes good sense to me.
> How exactly did you create the segfault? Just starting with -s and
Alistair Francis writes:
> Whoops, I thought I had already reviewed this commit.
You had provided quite extensive review with lots of useful comments,
but never added the magic tag for this commit :-)
--
-keith
signature.asc
Description: PGP signature
From: Kito Cheng
This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.
Verified GCC testsuite with newlib/semihosting.
Signed-off-by: Kito Cheng
Reviewed-by: Keith Packard
Message-Id: <20201214200713.3886611-7-kei..
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_a
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
Message-Id: <20201214200
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-b
This series adds support for RISC-V Semihosting, version 0.2 as
specified here:
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
This specification references the ARM semihosting release 2.0 as
specified here:
https://static.docs.arm.com/100863/0200/semihosting.pd
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-9-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-semi.c b
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-8-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3 files ch
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-10-kei...@keithp.com>
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
inde
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified use a new config variable,
CONF
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
Message-Id: <20201214200713.3886611-6-kei...@keithp
When checking whether there is a live gdb connection, code shouldn't
use 'gdbserver_state.init' as that value is set when the
gdbserver_state structure is initialized in init_gdbserver_state, not
when the gdb socket has a valid connection.
The 'handle_detach' function appears to use 'gdbserver_sta
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index b0648c3812..abc15bf219 100644
--- a/hw/semihosting/commo
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified use a new config variable,
CONF
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index b1368d945c..b0648c381
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-b
From: Kito Cheng
This could made testing more easier and ARM/AArch64 has supported on
their linux user mode too, so I think it should be reasonable.
Verified GCC testsuite with newlib/semihosting.
Signed-off-by: Kito Cheng
Reviewed-by: Keith Packard
---
linux-user/riscv/cpu_loop.c | 5 +
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3 files changed, 22 insertions(+)
diff --git a/hw/semihosting/comm
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
---
v2
Explicit
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_a
This series adds support for RISC-V Semihosting, version 0.2 as
specified here:
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
This specification references the ARM semihosting release 2.0 as specified here:
https://static.docs.arm.com/100863/0200/semihosting.pd
Alex Bennée writes:
> Hmm scratch that... it fails in a number of linux-user only builds with:
>
> /usr/bin/ld:
> libqemu-aarch64_be-linux-user.fa.p/linux-user_aarch64_cpu_loop.c.o: in
> function `cpu_loop':
> /builds/stsquad/qemu/build/../linux-user/aarch64/cpu_loop.c:133: undefined
> ref
Kito Cheng writes:
> Hi Keith:
>
> Thanks for your reply, but it seems like we need some more modification in
> linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in
> mail
> rather than attachment :)
Ah, I completely missed the attachment! So sorry. That applies cleanly
on
Kito Cheng writes:
> Hi Keith:
>
> Thanks for the patch, I've verified with newlib semihosting support
> which is contributed by Craig Blackmore from embecosm,
> and I would like to add semihosting to user mode, do you mind add this
> patch into this patch series?
I tried to add that already, bu
env->boot_info is only set in some ARM startup paths, so we cannot
rely on it to support the SYS_HEAPINFO semihosting function. When not
available, fallback to finding a RAM memory region containing the
current stack and use the base of that.
Signed-off-by: Keith Packard
---
hw/semihosting/commo
These are part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 16
include/qemu/timer.h | 2 ++
util/qemu-timer-common.c | 4
3 files changed, 22 insertions(+)
diff --git a/hw/semihosting/comm
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index 9a04d98e4e..fda0e714ef 100644
--- a/hw/semihosting/commo
Part of Semihosting for AArch32 and AArch64 Release 2.0
Signed-off-by: Keith Packard
---
hw/semihosting/common-semi.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c
index c84b0d906b..9a04d98e4
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_a
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified use a new config variable,
CONF
This series adds support for RISC-V Semihosting, version 0.2 as
specified here:
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
This specification references the ARM semihosting release 2.0 as specified here:
https://static.docs.arm.com/100863/0200/semihosting.pd
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-b
Commit 619985e937 (semihosting: defer connect_chardevs a little more
to use serialx) moved the call to qemu_semihosting_connect_chardevs
until after all of the serial devices were initialized to make
semihosting console configuration easier.
This change broke semihosting console input as the call
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-b
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_a
This series adapts the existing ARM semihosting code to be
target-independent, and then uses that to provide semihosting support
for RISC-V targets.
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified use a new config variable,
CONF
This makes all of the internal interfaces architecture-independent and
renames the internal functions to use the 'common_semi' prefix instead
of 'arm' or 'arm_semi'.
To do this, some new architecture-specific internal helper functions
were created:
static inline target_ulong
common_semi_a
This commit renames two files which provide ARM semihosting support so
that they can be shared by other architectures:
1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c
2. linux-user/arm/semihost.c -> linux-user/semihost.c
The build system was modified to reflect this change, but the
The public API is now defined in
hw/semihosting/common-semi.h. do_common_semihosting takes CPUState *
instead of CPUARMState *. All internal functions have been renamed
common_semi_ instead of arm_semi_ or arm_. Aside from the API change,
there are no functional changes in this patch.
Signed-off-b
This series first adapts the existing ARM semihosting code to be
architecture-neutral, then adds RISC-V semihosting support using that.
Patch 1/4 moves the ARM semihosting support code to common directories and
adapts the build system to match.
Patch 2/4 changes the public API to this code to use
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
The SiFive test device provides a mechanism for terminating the qemu
instance from the emulated system. This patch adds that device to the
sifive_u target, including constructing a suitable FDT node.
Signed-off-by: Keith Packard
---
hw/riscv/sifive_u.c | 15 +++
include/hw/ri
The SiFive test device provides a mechanism for terminating the qemu
instance from the emulated system. This patch adds that device to the
sifive_e target.
Signed-off-by: Keith Packard
---
hw/riscv/sifive_e.c | 4
include/hw/riscv/sifive_e.h | 1 +
2 files changed, 5 insertions(+)
The SiFive test device, which is already available in the qemu tree,
allows the system under emulation to shut down qemu. This is currently
used by OpenSBI to terminate QEMU at powerdown time. These two patches
add this device to the two sifive models.
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handl
'virtm' is a hardware target that is designed to be used for compiler
and library testing on Cortex-M processors. It supports all cortex-m
processors and includes sufficient memory to run even large test
cases.
Signed-off-by: Keith Packard
---
MAINTAINERS | 9 +++-
hw/arm/Makefile.obj
The size of the FPU registers is dictated by the 'f' and 'd' features,
not the core processor register size. Processors with the 'd' feature
have 64-bit FPU registers. Processors without the 'd' feature but with
the 'f' feature have 32-bit FPU registers.
Signed-off-by: Keith Packard
---
v2:
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