From: Kane-Chen-AS
This patch introduces a 'drive' property to the Aspeed OTP device,
allowing it to be backed by a block device. Users can now preload
OTP data via QEMU CLI using a block backend.
Example usage:
./qemu-system-arm \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
Reviewed-by: C??dric Le Goater
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 inser
From: Kane-Chen-AS
This patch adds a new machine parameter `otpmem` which creates a QOM
property alias on the aspeed_sbc device for the OTP drive.
Example usage:
./qemu-system-arm \
-machine ast2600-evb,otpmem=otp-drive \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
-
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a
From: Kane-Chen-AS
This patch series extends the QEMU model for the ASPEED OTP (One-Time
Programmable) memory device with block backend support and tighter
integration with the SoC and machine configuration.
The OTP model simulates a simple fuse array, used in ASPEED SoCs
for secure boot and con
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32-bi
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32-bi
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --
From: Kane-Chen-AS
This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.
If no external block backend is provided via the "dri
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c | 2 ++
include/hw/misc/aspeed_sbc.h | 2 ++
3 files c
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration, i
From: Kane-Chen-AS
This patch exposes a new "otpmem" machine parameter to allow users to
attach an OTP memory device to AST1030 and AST2600-based platforms.
The value of this parameter is passed as a QOM alias to the Secure Boot
Controller (SBC), enabling binding to an aspeed.otpmem device creat
From: Kane-Chen-AS
Introduce a functional test suite to validate the ASPEED OTP memory
device integration under different machine configurations.
The following cases are covered:
- AST2600 with blockdev + device + machine parameter (full binding)
- AST2600 fallback with no machine parameter
- AS
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads a 32
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage or boot-time configuration. The OTP memory can operate
with either:
- a file-backed backend via the 'drive' property,
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoCs (AST2600, AST1030).
The OTP model emulates a simple fuse array used for secure boot or
device config
From: Kane-Chen-AS
Introduce a QEMU model for ASPEED One-Time Programmable (OTP) memory.
This device provides:
- Bit-level irreversible programming (0→1 for even, 1→0 for odd)
- Read, program, and default-value initialization interfaces
- File-backed OTP content via machine parameter
- Trace sup
From: Kane-Chen-AS
Integrate the aspeed.otpmem backend with the ASPEED Secure Boot
Controller (SBC).
This patch adds command handling support in the SBC to read and program
the connected OTP memory using READ, WRITE, and PROG commands. It enables
basic interaction with OTP content for secure boo
From: Kane-Chen-AS
Expose an "otpmem" machine parameter to load an external OTP memory image
and enable OTP functionality in supported SoCs.
- Adds object property and backend connection logic for AST1030 and AST2600
- Allows disabling OTP feature via has_otpmem attribute
- Supports use cases in
From: Kane-Chen-AS
Dear reviewers,
This series introduces the ASPEED OTP (One-Time Programmable) memory model
and connects it to the SBC controller and AST10x0/AST2600 SoCs.
The OTP model supports irreversible bit programming, file-backed content,
and tracepoints for program conflict debugging.
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device (`aspeed.otpmem
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be generated
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the foundation
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and suppor
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and suppor
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the foundation
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device (`aspeed.otpmem
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be generated
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