From: Kane-Chen-AS
This patch introduces a 'drive' property to the Aspeed OTP device,
allowing it to be backed by a block device. Users can now preload
OTP data via QEMU CLI using a block backend.
Example usage:
./qemu-system-arm \
-blockdev driver=file,filename=otpmem.img,nod
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
Reviewed-by: C??dric Le Goater
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3
From: Kane-Chen-AS
This patch adds a new machine parameter `otpmem` which creates a QOM
property alias on the aspeed_sbc device for the OTP drive.
Example usage:
./qemu-system-arm \
-machine ast2600-evb,otpmem=otp-drive \
-blockdev driver=file,filename=otpmem.img,node-name=otp
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface thro
From: Kane-Chen-AS
This patch series extends the QEMU model for the ASPEED OTP (One-Time
Programmable) memory device with block backend support and tighter
integration with the SoC and machine configuration.
The OTP model simulates a simple fuse array, used in ASPEED SoCs
for secure boot and
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads
Hi Cédric,
Got it, I'll rename the type to "aspeed-otp" as suggested to support the global
property syntax.
Thanks for the clarification!
Best regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, June 30, 2025 2:28 PM
> To: Kane Chen
, 2025 2:18 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
> Cc: Troy Lee
> Subject: Re: [PATCH v3 1/3] hw/misc/aspeed_otp: Add OTP device model with
> f
From: Kane-Chen-AS
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: reads
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff
From: Kane-Chen-AS
This patch introduces a QEMU model of the ASPEED One-Time Programmable
(OTP) memory, used for secure fuse storage. The model simulates a
word-addressable OTP region with a memory-like interface via a dedicated
AddressSpace.
If no external block backend is provided via the
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration
instance? Or would it be acceptable to
instantiate it internally and avoid exposing it via -device?
Thanks again for your time and feedback.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, June 27, 2025 2:52 PM
> To: Kane Chen ; Peter Maydell
&g
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: re
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface thro
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration
Hi Cédric,
Thanks for your feedback. I will move the OTP implementation to `hw/nvram/` as
suggested, and adjust the related code accordingly.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, June 26, 2025 4:23 PM
> To: Kane Chen ; P
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface thro
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: re
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration
ns.
Best Regards,
Kane
> -Original Message-
> From: Peter Maydell
> Sent: Wednesday, June 25, 2025 6:26 PM
> To: Kane Chen
> Cc: Cédric Le Goater ; Steven Lee
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface thro
, I'm wondering whether I should still use the "RFC" tag for the next
version of the patch.
Would you recommend keeping the "RFC" tag, or is it appropriate to drop it at
this point?
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sen
, June 24, 2025 2:28 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
> Cc: Troy Lee
> Subject: Re: [RFC v6 1/3] hw/misc/aspeed_otp: Add ASPEED OTP memory
>
From: Kane-Chen-AS
The has_otpmem attribute is enabled in the SBC subclasses for AST2600
to control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
---
hw/arm/aspeed_ast2600.c | 2 +-
hw/misc/aspeed_sbc.c | 2 ++
include/hw/misc/aspeed_sbc.h | 2 ++
3 files
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: re
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoC (AST2600).
The OTP model emulates a simple fuse array used for secure boot or
device configuration
t: Friday, June 20, 2025 1:44 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
> Cc: Troy Lee
> Subject: Re: [RFC v5 0/4] Add QEMU model for ASPEED OTP
From: Kane-Chen-AS
This patch exposes a new "otpmem" machine parameter to allow users to
attach an OTP memory device to AST1030 and AST2600-based platforms.
The value of this parameter is passed as a QOM alias to the Secure Boot
Controller (SBC), enabling binding to an aspeed.otp
From: Kane-Chen-AS
Introduce a functional test suite to validate the ASPEED OTP memory
device integration under different machine configurations.
The following cases are covered:
- AST2600 with blockdev + device + machine parameter (full binding)
- AST2600 fallback with no machine parameter
From: Kane-Chen-AS
This patch connects the aspeed.otpmem device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming flows.
The following OTP commands are supported:
- READ: re
From: Kane-Chen-AS
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage or boot-time configuration. The OTP memory can operate
with either:
- a file-backed backend via the 'drive
From: Kane-Chen-AS
This patch series introduces a QEMU model for the ASPEED OTP (One-Time
Programmable) memory, along with its integration into the Secure Boot
Controller (SBC) and supported SoCs (AST2600, AST1030).
The OTP model emulates a simple fuse array used for secure boot or
device
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 27, 2025 3:02 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
Hi Cédric,
Sure, I’ll submit a version that removes the more specific operations and
focuses on the initial implementation first.
Thanks again for the guidance!
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 27, 2025 5:36 PM
> T
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 27, 2025 4:12 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
From: Kane-Chen-AS
Introduce a QEMU model for ASPEED One-Time Programmable (OTP) memory.
This device provides:
- Bit-level irreversible programming (0→1 for even, 1→0 for odd)
- Read, program, and default-value initialization interfaces
- File-backed OTP content via machine parameter
- Trace
From: Kane-Chen-AS
Integrate the aspeed.otpmem backend with the ASPEED Secure Boot
Controller (SBC).
This patch adds command handling support in the SBC to read and program
the connected OTP memory using READ, WRITE, and PROG commands. It enables
basic interaction with OTP content for secure
From: Kane-Chen-AS
Expose an "otpmem" machine parameter to load an external OTP memory image
and enable OTP functionality in supported SoCs.
- Adds object property and backend connection logic for AST1030 and AST2600
- Allows disabling OTP feature via has_otpmem attribute
- Supports
From: Kane-Chen-AS
Dear reviewers,
This series introduces the ASPEED OTP (One-Time Programmable) memory model
and connects it to the SBC controller and AST10x0/AST2600 SoCs.
The OTP model supports irreversible bit programming, file-backed content,
and tracepoints for program conflict debugging
Hi Cédric,
> > > +{
> > > +AspeedSBCState *s = ASPEED_SBC(opaque);
> > > +uint32_t otp_addr, data, otp_offset;
> > > +bool is_data = false;
> > > +Error *local_err = NULL;
> > > +
> > > +assert(s->otpmem);
> > > +
> > > +otp_addr = s->regs[R_ADDR];
> > > +if (otp_addr <
.
If you would prefer to have a message logged, please let me know.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, April 29, 2025 5:06 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery
Hi Cédric,
I may have misunderstood the otpmem machine option. Please correct me if I am
wrong.
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 28, 2025 7:01 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> J
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 28, 2025 3:41 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 28, 2025 3:21 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 28, 2025 3:06 PM
> To: Kane Chen ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and
Thursday, April 17, 2025 6:06 PM
> To: Kane Chen ; Kane Chen via
> ; Cédric Le Goater ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Kane Chen
>
&
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be
c Le Goater
> Cc: Kane Chen ; Philippe Mathieu-Daudé
> ; Peter Maydell ; Steven Lee
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
> ; qemu-block ; Troy Lee
>
> Subject: Configuring onboard devices, in
nal Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 5:55 PM
> To: Kane Chen ; Philippe Mathieu-Daudé
> ; Peter Maydell ; Steven Lee
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC h
review.
Best Regards,
Kane
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, April 4, 2025 9:54 PM
> To: Philippe Mathieu-Daudé ; Kane Chen
> ; Peter Maydell ;
> Steven Lee ; Troy Lee ;
> Jamin Lin ; Andrew Jeffery
> ; Joel Stanley ; open
> list:
This patch adds the OTP memory and its controller as part of the
Secure Boot Controller (SBC) device model. The OTP memory content is
persisted to a file named 'otpmem', which is created if it does not
already exist.
Signed-off-by: Kane-Chen-AS
---
hw/misc/aspeed_sbc.c
programmed from within the guest
OS via a software utility.
Kane-Chen-AS (1):
hw/misc/aspeed_sbc: Implement OTP memory and controller
hw/misc/aspeed_sbc.c | 304 +++
include/hw/misc/aspeed_sbc.h | 14 ++
2 files changed, 318 insertions(+)
--
2.43.0
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