[PATCH 0/3] risc-v: Add ISA extension smcntrpmf support

such that the implemented firmware support [2] can work without causing unnecessary illegal instruction exceptions. [1] https://github.com/riscv/riscv-smcntrpmf [2] https://github.com/rivosinc/opensbi/tree/dev/kaiwenx/smcntrpmf_upstream Kaiwen Xue (3): target/riscv: Add cycle & instret privi

[PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties

This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

[PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support

QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: Kaiwen Xue Signed

[PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions

This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Kaiwen Xue --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv