Hi,
Is there a way to reproduce this issue? I have tried with the
available reproducer but it doesn't seem to work.
It would be really helpful to improve my understanding of qemu and I
can help in testing the patch-sets additionally.
Thanks
T K Sourab
On Tue, Jun 24, 2025 at 6:43 AM Phi
Good
Ajuz
e?
> Something in here?
> https://github.com/qemu/qemu/blob/master/linux-user/signal.c#L335
>
> Nothing jumps out with a quick look though
>
> Alistair
>
> >
> >
> >
> > --
> > Andreas K. Hüttel
> > dilfri...@gentoo.org
> > Gento
8) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
waitid(P_ALL, -1, {}, WNOHANG|WEXITED|WSTOPPED|WCONTINUED, NULL) = 0
(...)
--
Andreas K. Hüttel
dilfri...@gentoo.org
Gentoo Linux developer
(council, toolchain, base-system, perl, libreoffice)
signature.asc
Description: This is a digitally signed message part.
Am Donnerstag, 14. September 2023, 03:22:49 CEST schrieb Andreas K. Huettel:
> > > https://lists.gnu.org/archive/html/bug-bash/2023-09/msg00119.html
> > > ^ Here I'm trying to find out more.
> > >
> > > Bash tests apparently indicate that argv[0] is over
ailing with ENOENT, which is not one of the documented
> errors for wait(2):
So maybe another point to look at would be the origin of the return
values of wait, and whether that's wired correctly for rv32...
[1] https://savannah.gnu.org/bugs/?64664
--
Andreas K. Hüttel
dilfri...@gentoo.or
Am Mittwoch, 13. September 2023, 10:06:01 CEST schrieb Michael Tokarev:
> 13.09.2023 04:41, LIU Zhiwei wrote:
> >
> > On 2023/9/13 6:31, Andreas K. Huettel wrote:
> ..
> >> * Something seems wrong in the signal handling (?):
> >
> > If it is wrong for sig
/machines/riscv32/usr/bin/qemu-riscv32 -version
qemu-riscv32 version 8.1.0
Copyright (c) 2003-2023 Fabrice Bellard and the QEMU Project developers
[*] https://www.gentoo.org/downloads/#riscv
--
Andreas K. Hüttel
dilfri...@gentoo.org
Gentoo Linux developer
(council, toolchain, base-system, perl,
d, 29 insertions(+), 13 deletions(-)
v3 - drop fallback to MFFS for 3.0 ISA to match hardware
v2 - switch to use decodetree pattern groups per feedback
Reviewed-by: Matheus Ferst
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
ISA says and keep the same behavior as the
hardware. Again, sorry for the delayed response.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 05/05/2023 12:23, Richard Henderson wrote:
On 5/4/23 18:17, Matheus K. Ferst wrote:
On 04/05/2023 08:01, Richard Purdie wrote:
The following commits changed the code such that these instructions
became invalid
on pre 3.0 ISAs:
bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move
, return false and let the pattern group
* select the correct instruction.
*/
return false;
}
That way, I believe it'll be easier to add more MFFS variants in the
future without thinking too much about the behavior in previous versions
of Power ISA.
Thanks,
Matheus K.
failures after ~200
iterations of this test, so we may have more problems to tackle here.
However, it's not a CPU abort anymore, the second QEMU invocation exits
with zero without writing anything to the console.
All that said, patches 1-26 are queued in ppc-next.
On 10/20/22 10:40,
ogether.
Nice catch. I guess we need a gen_icount_io_start before calling
helper_ppc_maybe_interrupt, so maybe it's better to make a
gen_ppc_maybe_interrupt that calls icount and the helper. I'll give it a
bit more testing and re-spin the series.
Thanks,
Matheus K. Ferst
In
gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]);
> #else
Since all CPUs with ISA207S are 64-bit, it shouldn't make any difference
in this context, but someone might use this code as an example, so it's
better to have these checks in the correct order. Do you want me to
resend with this change?
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
l = 168355058
>
> // Output before the fix, note the messed layout:
> //
> // f_type = 0x10009123683e
> // f_bsize = 723302085239504896
> // f_blocks = 168355058
> // f_bfree = 2250817541779750912
> // f_bavail = 1099229433104
> ```
>
> Fixes: 1f63019632 ("l
any
> other 32-bit ABI that passes 64-bit arguments in pairs of GPRs. Fix by
> excluding TARGET_ABI_MIPSN32 from various TARGET_ABI_BITS == 32 checks.
>
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/1238
> Signed-off-by: WANG Xuerui
> Cc: Philippe Mathieu-Daudé
>
CR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL)) ==
PPC_DECR_UNDERFLOW_TRIGGERED, i.e., PPC_DECR_UNDERFLOW_TRIGGERED is set
and PPC_DECR_UNDERFLOW_LEVEL is clear. All Book3S CPU have a level
triggered interrupt, so the method return false.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldo
|scp (s)| iperf (MB/s) |
+-+---+-+
|PowerNV master | 142.73 ± 8.38 | 924.34 ± 353.93 |
|PowerNV patch series | 145.75 ± 9.18 | 874.52 ± 286.21 |
+-+---+-+
Thanks
eep will use gen_exception_nip with
this value as the last argument.
+}
+
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
env->pending_interrupts &= ~PPC_INTERRUPT_MCK;
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index
;re not
checking for ISA 3.00 on msgsync... I'll keep these interrupts in v3 and
send a separate patch fixing the instruction flags.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
return PPC_INTERRUPT_DECR;
Tḧanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
E)) {
+return PPC_INTERRUPT_EBB;
+}
+}
+}
+
+return 0;
+}
+
static int ppc_pending_interrupt_legacy(CPUPPCState *env)
{
bool async_deliver;
@@ -1793,6 +1950,9 @@ static int ppc_pending_interrupt_legacy(CPUPPCState *env)
static int ppc_pending_interrupt(CPUPPCState *env)
{
switch (env->excp_model) {
+case POWERPC_EXCP_POWER9:
+case POWERPC_EXCP_POWER10:
+return ppc_pending_interrupt_p9(env);
default:
return ppc_pending_interrupt_legacy(env);
}
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
uption code in the following patches is acceptable, I'm planning
to add methods for all CPUs and remove ppc_pending_interrupt_legacy in
future versions of this patch series.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Avi
env->pending_interrupts == 0) {
+cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+}
+return true;
}
#endif /* !CONFIG_USER_ONLY */
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
acOS images also.
Thanks,
C.
Unfortunately, I can't test with MacOS :/
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
;
+}
if (ctx->le_mode) {
gen_align_no_le(ctx);
--
2.36.1
Since the remaining code in this branch is dead code in user-mode, I'd
personally prefer the v1 approach, but the difference is unlikely to
have any meaningful impact, so either way is good.
Revie
" TARGET_FMT_lu
"\n",
cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env),
cpu_ppc_load_decr(env));
#else
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
"\n",
care about, with env->tb_env being NULL, IMO
let's fix the bug and move on.
I'll send a v2 fixing the other segfault in monitor, and then I guess we
have a complete solution. Thanks Daniel and David for the feedback.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
uot;, ri->gregs[38]);
-fprintf(f, "\tmq : %16lx\n", ri->gregs[39]);
-fprintf(f, "\ttrap : %16lx\n", ri->gregs[40]);
-fprintf(f, "\tdar: %16lx\n", ri->gregs[41]);
-fprintf(f, "\tdsisr : %16lx\n", ri->gregs[42]);
-fprintf(f, "\tresult : %16lx\n", ri->gregs[43]);
-fprintf(f, "\tdscr : %16lx\n\n", ri->gregs[44]);
-
-for (i = 0; i < 16; i++) {
-fprintf(f, "\tf%2d: %016lx\tf%2d: %016lx\n", i, ri->fpregs[i],
-i + 16, ri->fpregs[i + 16]);
+sep = "\n";
+for (i = j = 0; i < 32; i++) {
+fprintf(f, "%s%*s%d: %016lx",
+sep, 6 - (i < 10 ? 1 : 2), "f", i, ri->fpregs[i]);
+sep = (++j & 1 ? " " : "\n");
}
-fprintf(f, "\tfpscr: %016lx\n\n", ri->fpscr);
+fprintf(f, "\n%6s: %016lx\n", "fpscr", ri->fpscr);
for (i = 0; i < 32; i++) {
-fprintf(f, "vr%02d: %8x, %8x, %8x, %8x\n", i,
+fprintf(f, "%*s%d: %08x %08x %08x %08x\n",
+6 - (i < 10 ? 1 : 2), "vr", i,
ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1],
ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]);
}
--
2.34.1
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
, 11 insertions(+), 21 deletions(-)
Hi Richard,
Reviewed-by: Matheus Ferst
It seems that the series is missing some r-b tags that Alex sent in v3
(e.g. https://lore.kernel.org/qemu-devel/871rm590sg@linaro.org/).
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <h
hlighting it.
Thanks again!
Fred
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
sts recently and didn't notice this behavior.
Could you share your QEMU command line with us? Did you build QEMU with
any debug option or sanitizer enabled?
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
(TCGv_ptr d, TCGv_ptr s)
+{
+glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s);
+}
+
static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
intptr_t b, TCGLabel *label)
{
--
2.34.1
Reviewed-by: Matheus Ferst
--
Matheus K. Ferst
Instituto de
uot; for qemu-system-ppc too, so maybe something like
> /* Update the 'max' alias to the latest CPU model */
> #if defined(TARGET_PPC64)
> { "max", "power10_v2.0" },
> #else
> { "max", "7457a_v1.2" },
> #endif
Or some other CPU which is considered the max for 32-bit...
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
think I have access to a power9 machine to test this with
either, so I might want a tested-by from someone who does.
--js
Unfortunately, none of our POWER9 machines had a firmware old enough to
be affected by this issue. The closest I can test is a nested KVM-HV
with L0 using cap-cfpc=broken, s
n the final
version?
Let's not add anything that we don't have a need for.
It may eventually be needed by RISC-V RV128, but we can add it then.
r~
Thanks for your comments and review. I'll send an alternative version of
this RFC using Int128.
--
Matheus K. Ferst
Instituto d
offset 0x24 for
the here applicable ELFCLASS32).
See-also: ace3d65459
Signed-off-by: Andreas K. Hüttel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: WANG Xuerui
Cc: Laurent Vivier
Cc: WANG Xuerui
Cc: Richard Henderson
Cc: Alex Bennee
Cc: Philippe Mathieu-Daudé
Closes: https://gitlab.com/qemu
> Closes: https://gitlab.com/qemu-project/qemu/-/issues/939
> Signed-off-by: WANG Xuerui
> Cc: Philippe Mathieu-Daudé
> Cc: Aurelien Jarno
> Cc: Jiaxun Yang
> Cc: Aleksandar Rikalo
> Cc: Andreas K. Hüttel
> ---
Tested-by: Andreas K. Huettel
> target/mips/cpu-
0x0, 0x0, 0x0, 0x0,
| },
| .e_type = 2 , /* (ET_EXEC) */
| .e_machine = 8 , /* (EM_MIPS) */
| .e_version = 1 , /* (EV_CURRENT) */
| (...)
Signed-off-by: Andreas K. Hüttel
---
scripts/qemu-binfmt-conf.sh | 4 ++--
1 file changed, 2 insertions(+)
This information is given by the EF_MIPS_ABI2 (0x20) bit in the
e_flags field of the ELF header (a 4-byte value at offset 0x24 for
the here applicable ELFCLASS32).
See-also: https://www.mail-archive.com/qemu-devel@nongnu.org/msg732572.html
Signed-off-by: Andreas K. Hüttel
---
scripts/qemu
Re-sending v3 unchanged as requested.
The first patch has already been submitted earlier and is unchanged from v2.
The second patch extends it and resolves issue 843, "duplicate magic mips
patterns".
Tested with various self-bootstrapped Gentoo chroots and in production on
the Gentoo release eng
This information is given by the EF_MIPS_ABI2 (0x20) bit in the
e_flags field of the ELF header (a 4-byte value at offset 0x24 for
the here applicable ELFCLASS32).
See-also: https://www.mail-archive.com/qemu-devel@nongnu.org/msg732572.html
Signed-off-by: Andreas K. Hüttel
---
scripts/qemu
0x0, 0x0, 0x0, 0x0,
| },
| .e_type = 2 , /* (ET_EXEC) */
| .e_machine = 8 , /* (EM_MIPS) */
| .e_version = 1 , /* (EV_CURRENT) */
| (...)
Signed-off-by: Andreas K. Hüttel
---
scripts/qemu-binfmt-conf.sh | 4 ++--
1 file changed, 2 insertions(+)
Two patches; the first one has been under review before, the second builds
on it and extends the binfmt-misc magic to differentiate between o32 and
n32 binaries (see also issue 843).
ould use gen_hvpriv_exception in those cases, so we have
POWERPC_EXCP_HV_EMU with POWERPC_EXCP_PRIV | something.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
: K. Lange
---
ui/gtk.c | 4
1 file changed, 4 insertions(+)
diff --git a/ui/gtk.c b/ui/gtk.c
index a8567b9ddc..8675ae76fa 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -958,6 +958,10 @@ static gboolean gd_button_event(GtkWidget *widget,
GdkEventButton *button,
return TRUE
0x0, 0x0, 0x0, 0x0,
| },
| .e_type = 2 , /* (ET_EXEC) */
| .e_machine = 8 , /* (EM_MIPS) */
| .e_version = 1 , /* (EV_CURRENT) */
| (...)
Signed-off-by: Andreas K. Hüttel
---
v2: Add the same fix for little endian as for big endian
scripts/qemu
srd 0, %2" and "mfvsrd %0, 0" were correct, I'm just
changing from VSR 0 to VSR 32 to allow the clobber with Clang, but GCC
doesn't seem to have this limitation with ELFv1.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.b
tch series since
it's not test-related.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
= 2 , /* (ET_EXEC) */
| .e_machine = 8 , /* (EM_MIPS) */
| .e_version = 1 , /* (EV_CURRENT) */
| (...)
Signed-off-by: Andreas K. Hüttel
---
scripts/qemu-binfmt-conf.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/qemu-b
.
Patches without review: 4, 24, 26, 27, 34, 35, 38, 40, 44-46
I think we are done.
Applied to ppc-7.0.
Thanks,
C.
We still had some minor fixes, but I guess we can send in a follow-up patch.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Anali
On 23/02/2022 19:19, Richard Henderson wrote:
On 2/23/22 11:43, Matheus K. Ferst wrote:
Note that rotlv does the masking itself:
/*
* Expand D = A << (B % element bits)
*
* Unlike scalar shifts, where it is easy for the target front end
* to include the modulo as part of the exp
derstood. To check != 0 we'll need a temp to
hold n&64. We could use tmp here, but we'll need another one in patch
22. Is that right?
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
{
+ INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
+ INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
+ };
Where is sari used?
I'll remove in v5.
[1] Section 5.3 of
https://www.intel.com/content/dam/develop/external/us/en/documents/36945
Thanks,
Matheus K. Ferst
Insti
Ping.
All patches reviewed and the series still applies to master with no
conflicts.
On 13/01/2022 14:04, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
In the review of 66c6b40aba1, Richard Henderson suggested[1] using
"trap" instead of ".long 0x0" to generate the signal to test
On 17/02/2022 09:46, Matheus K. Ferst wrote:
On 17/02/2022 05:09, Cédric Le Goater wrote:
On 2/8/22 21:31, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
LLVM/Clang doesn't like inline asm with __int128, use a vector type
instead.
Signed-off-by: Matheus Ferst
---
Alternat
e be using :
#if BYTE_ORDER == LITTLE_ENDIAN
instead ?
I guess it is better, I'll send a v2.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 14/02/2022 12:14, Alex Bennée wrote:
"Matheus K. Ferst" writes:
On 11/02/2022 13:03, Alex Bennée wrote:
This builds vectorised versions of sha512 to exercise the vector code:
- aarch64 (AdvSimd)
- i386 (SSE)
- s390x (MVX)
- ppc64 (vector)
Signed-off-by: A
_op_shli_vec, INDEX_op_sari_vec, 0
+ };
Therefore no vecop_list required (cmp itself is mandatory).
Without vecop_list, we hit the assert in tcg_assert_listed_vecop, which
is called from tcg_gen_cmp_vec. Am I missing something?
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.
this test for big-endian too?
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
e float64r32_muladd
tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf
and see how we can address the LLVM support for P10 later ?
The problems with bcdsub.c are not resolved for Clang < 14, but I guess
it's ok to merge anyway.
Thanks,
Matheus K. Ferst
Institut
x-gnu-gcc"}
: ${cross_cc_s390x="s390x-linux-gnu-gcc"}
: ${cross_cc_sh4="sh4-linux-gnu-gcc"}
--
2.34.1
The patch is fine, but some PPC tests are not compiling with Clang. I've
sent an RFC about these issues:
https://lists.gnu.org/archive/html/qemu-ppc/2022-02/msg00116.html
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
Ping.
The based-on series is already on master, only patch 3 is missing review.
On 13/01/2022 14:04, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
In the review of 66c6b40aba1, Richard Henderson suggested[1] using
"trap" instead of ".long 0x0" to generate the signal to test XER
sav
to use a do/while() loop. This will keep the
same semanting as the existing while() loop does and the compiler will
understand that 'taddr' will be initialized at least once.
Suggested-by: Matheus K. Ferst
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573
Signed-off-by: Daniel Henr
hw/pci-host/pnv_phb4.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Matheus Ferst
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 27/01/2022 09:09, Daniel Henrique Barboza wrote:
On 1/27/22 08:41, Matheus K. Ferst wrote:
On 26/01/2022 17:14, Daniel Henrique Barboza wrote:
The 'taddr' variable is left unintialized, being set only inside the
"while ((lev--) >= 0)" loop where we get the TCE addre
ce_memory, taddr, &tce,
@@ -1288,7 +1296,7 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds,
hwaddr addr,
}
sh -= tbl_shift;
base = tce & ~0xfffull;
-}
+} while ((lev--) >= 0);
The same comments from the other patch app
to use a do/while() loop. This will keep the
same semanting as the existing while() loop does and the compiler will
understand that 'taddr' will be initialized at least once.
Suggested-by: Matheus K. Ferst
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573
Signed-off-by: Daniel
memory_read(&address_space_memory, taddr, &tce,
/* ... */
}
sh -= tbl_shift;
base = tce & ~0xfffull;
} while (lev >= 0);
Otherwise, I think we'll need to initialize tce too.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 24/01/2022 20:13, Philippe Mathieu-Daudé via wrote:
This code is easier to review using the load/store API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/misc/macio/cuda.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
Reviewed-by: Matheus Ferst
--
Matheus K. Ferst
ccording to docs/devel/migration.rst, .minimum_version_id_old is
ignored if no load_state_old handler is provided, I think we can drop it
too.
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
--
2.31.1
Thanks,
Matheus K. Ferst
Instituto de P
rce_sig_fault. (I have a pending patch set to convert all
other instances;
hopefully that can be merged soon...)
I'll send v2 with a Based-on
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer
fix was
> > incomplete.
>
> ping
>
Sorry I can't say anything about this.
The hangs that I experience seem to be unrelated to the patch (no improvement,
but also no worsening).
--
Andreas K. Hüttel
dilfri...@gentoo.org
Gentoo Linux developer
(council, qa, toolch
ot;mtvsrd 0, %2\n\t"
"mtvsrd 1, %3\n\t"
"xxmrghd 0, 0, 1\n\t"
INSN " 0, 0\n\t"
"mfvsrd %0, 0\n\t"
"xxswapd 0, 0\n\t"
"mfvsrd %1, 0\n\t"
: "=r" (th), "=r" (tl)
: "r"
ET_SIGCHLD:
> > tinfo->_sifields._sigchld._pid = info->si_pid;
> > tinfo->_sifields._sigchld._uid = info->si_uid;
> > -tinfo->_sifields._sigchld._status = info->si_status;
> > + if (si_code == CLD_EXITED)
> &g
On 15/12/2021 12:55, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
On 12/13/21 21:15, Matheus K. Ferst wrote:
On 13/12/2021 09:36, Philippe Mathieu-Daudé wrote:
On 12/13/21 13:13, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The non-signalling versions of VSX scalar
e non-arithmatic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.
Signed-off-by: Matheus Ferst
Applied to ppc-next.
Thanks,
C.
Hi Cédric,
Alex requested some changes in the test part, could you drop this patch
for now?
Thanks,
Math
asm("xscvdpspn %x0, %x1\n\t"
: "=wa" (t)
: "wa" (b << 64));
printf("0x%016" PRIx64 "%016" PRIx64 "\n",
(uint64_t)(t >> 64), (uint64_t)t);
return 0;
}
Why not add this test in tests/tcg/ppc64l
l send a v2.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
x->opcode) + 32);
-gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
-tcg_temp_free_i32(opc);
+REQUIRE_INSNS_FLAGS2(ctx, ISA310);
It's actually ISA300. We'll send a v2 fixing this.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Anal
float_madds and float_convs
after fixing the bugs required to make the tests pass.
With this series and few other VSX instructions[1], QEMU now passes the
GLibc math test suite.
Tested-by: Matheus Ferst
[1] https://github.com/PPC64/qemu/tree/ferst-tcg-xsmaddqp (WIP)
Thanks,
Matheus K. Ferst
e and saving
the output (e.g.: ./float_convs > float_convs.ref).
However, both tests currently fail. I guess it's related to
https://bugs.launchpad.net/qemu/+bug/1841592, but I'm not sure if the
comments on this bug are still valid/up-to-date.
--
Matheus K. Ferst
Instituto de Pesquis
ase here, the helper was just renamed. The value of "n" comes
from ctz64(mask) and mask == 0 is a trivial case handled before anything
else.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
build this
commit for
PPC32, and I also found errors relating to undefined times_* functions
during bisection.
REQUIRE_FPU and the times_* functions come from the DFP patch series, in
which this series is based-on, so "target/ppc: Introduce REQUIRE_FPU"
was supposed to be merged be
On 08/11/2021 17:03, Daniel Henrique Barboza wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de
e-mail suspeito entre imediatamente em contato com o DTI.
On 11/8/21 16:48, Matheus K. Ferst wrote
if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) {
+env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE;
+env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
+}
+
+/* Fire the PMC hardware exception */
+ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1);
}
/* This helper assumes that
pmu_base_time and leave */
+env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+return;
+}
+
+pmu_start_overflow_timers(env);
}
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
--
2.31.1
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <htt
new_FC = false), set the new base_time for future cycle
+ * calculations.
+ */
+if (curr_FC != new_FC) {
+if (!curr_FC) { > +pmu_update_cycles(env);
+} else {
+start_cycle_count_session(env);
+}
+}
+}
--
Matheus K. Ferst
Instituto de Pe
So we still shift 63+1 bits when there are no leading zeros and shift 0
bits when it's all zeros.
Either way,
Reviewed-by: Richard Henderson
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaime
| 2 +-
target/ppc/cpu.h | 3 +++
target/ppc/fpu_helper.c| 41 ++
target/ppc/helper.h| 1 +
target/ppc/translate/fp-impl.c.inc | 6 ++---
5 files changed, 49 insertions(+), 4 deletions(-)
--
2.31.1
--
On 26/10/2021 15:45, Paul A. Clarke wrote:
On Tue, Oct 26, 2021 at 09:58:15AM -0700, Richard Henderson wrote:
On 10/26/21 7:33 AM, Matheus K. Ferst wrote:
It says that "if UIM is greater than N, the result is undefined." My
first read was also that the outcome is "boundedly un
helper receives i64 because it's also used by Vector Insert From VSR
in patch 17. We can drop the ifdef and always tcg_gen_extu_tl_i64 though.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
M is greater than N, the result is undefined." My
first read was also that the outcome is "boundedly undefined," but I
guess it can be understood as "the resulting value in VRT will be
undefined" (like when the pseudo-code uses "VRT <- 0x_..._"), in
w
should receive i64 and cannot be inside an ifdef(TARGET_PPC64). I'll add
this info to the commit message.
If we dismiss the possibility of a future 32-bits implementation of
PowerISA v3.1, we can move the helper inside the ifdef and add
REQUIRE_64BITS in vclzdm/vctzdm (and vcfuged, vpdepd,
longer apply cleanly. Do you have a branch you can
publish in the meantime?
r~
I forgot to mention that it's also based on Gibson's ppc-for-6.2. The
branch is available on
https://github.com/PPC64/qemu/tree/ppc-isa31-review
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <
x27;ll see if I can fix that in
another patch, and then we can change the test to use trap.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 24/09/2021 11:41, Daniel Henrique Barboza wrote:
On 9/22/21 08:24, Matheus K. Ferst wrote:
On 03/09/2021 17:31, Daniel Henrique Barboza wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você
possa confirmar o remetente e saber que o conteúdo é seguro. Em caso
de e
red content of the SPR to problem state. It might be better to
call the helper directly or create another method that takes a TCGv as
an argument and call it from spr_write_MMCR0_ureg and spr_write_MMCR0.
tcg_temp_free(t0);
tcg_temp_free(t1);
--
2.31.1
--
Matheus K. Ferst
Inst
onitor Mode
+ * Control Register 2, p. 1316, third paragraph.
+ */
+gen_load_spr(t0, SPR_POWER_MMCR2);
+tcg_gen_andi_tl(t0, t0, 0x402010080402UL);
+tcg_gen_mov_tl(cpu_gpr[gprn], t0);
+
+tcg_temp_free(t0);
+}
+
#if defined(TARGET_PPC64) && !defined(CONFIG_US
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