Wow, a full 3 years later!
Well, better late than never...
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not throw SIGILL
Status in QE
Yes, that seems to work nicely, at least as far as CMOV itself is
concerned.
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not throw SIG
The CMOV feature bit (bit 15 of EDX) should affect availability of the
following instructions:
CMOVcc (0F 40 -> 0F 4F)
FCMOVcc (DA C0 -> DA DF and DB C0 -> DB DF)
FCOMI family (DB E8 -> DB F7 and DF E8 -> DF F7)
HTH
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> Incidentally, if you're using KVM acceleration then these
> instructions won't fault in that setup because the host CPU
> hardware doesn't provide a means for trapping them.
This I already understood, and we made sure that we were running with
the TCG backend.
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> Actually, we do do testing of feature bits for things like SSE2,
3DNow!, and so on -- it looks like we just missed cmov.
That's encouraging to hear - I hadn't specifically tested for the
behaviour in the other cases I described, just extrapolated.
Is there a good chance that the CMOV thing will
Public bug reported:
We encountered a bug in another package that caused it to include CMOV
instructions when targetting i486, resulting in an inability to run the
package on real i486 and i586 hardware. We then attempted to use QEMU
to reproduce the bug for easier debugging, since most developer
