On Tue, 15 Jul 2025 10:01:21 -0700
Nicolin Chen wrote:
> On Tue, Jul 15, 2025 at 11:29:41AM +0100, Jonathan Cameron wrote:
> > > +if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,
> > > + IOMMU_VIOMMU_TYPE_ARM_SMMUV3,
> > > +
On Mon, 14 Jul 2025 16:59:41 +0100
Shameer Kolothum wrote:
> Now user can set "accel=on". Have fun!
>
> Signed-off-by: Shameer Kolothum
Hard to argue with this one ;)
Reviewed-by: Jonathan Cameron
> ---
> hw/arm/smmu-common.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm
On Mon, 14 Jul 2025 16:59:40 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE
On Mon, 14 Jul 2025 16:59:39 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Use the provided smmuv3-accel helper functions to issue the
> invalidation commands to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-internal.h | 11 +++
On Mon, 14 Jul 2025 16:59:38 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Helpers will batch the commands and issue at once to host SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-accel.c| 65 +
On Mon, 14 Jul 2025 16:59:34 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
>(Devices behind the same physical SMMU should share an S2 HWPT)
> -Else,
> Allocate a viommu with the nested parent S2
On Mon, 14 Jul 2025 16:59:32 +0100
Shameer Kolothum wrote:
> Accelerated SMMUv3 is only useful when the device can take advantage of
> the host's SMMUv3 in nested mode. To keep things simple and correct, we
> only allow this feature for vfio-pci endpoint devices that use the iommufd
> backend. We
On Mon, 14 Jul 2025 16:59:31 +0100
Shameer Kolothum wrote:
> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel
> SMMUv3 will have different handling for those ops callbacks
> in subsequent patches.
>
> The "accel" property is not yet added, so users cannot set it at this
> point. It will
On Mon, 14 Jul 2025 16:59:30 +0100
Shameer Kolothum wrote:
> Allows to retrieve the PCIIOMMUOps based on the SMMU type. This will be
> useful when we add support for accelerated SMMUV3 in subsequent patches
> as that requires a different set of callbacks for iommu ops.
>
> No special handling is
On Mon, 14 Jul 2025 16:59:29 +0100
Shameer Kolothum wrote:
> Subsequent patches for smmuv3 accel support will make use of this.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
Various trivial things inline. In general looks fine.
J
> ---
> hw/ar
On Mon, 14 Jul 2025 16:59:28 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate an iommufd device's virtual device (in the user
> space) per a viommu instance.
Same trivial suggestion as in patch 1. Also feel free to ignore.
On Mon, 14 Jul 2025 16:59:27 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Add a helper to allocate a viommu object.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Eric Auger
> Signed-off-by: Shameer Kolothum
One trivial comment inline. Feel free to ignore.
> ---
> backends/iomm
On Mon, 14 Jul 2025 10:04:44 +0200
Eric Auger wrote:
> This series enables ACPI PCI hotplug/hotunplug on ARM.
> It is not enabled by default and ACPI PCI hotplug can
> be selected by setting:
>
> -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
>
> Expected benefits should be similar t
From: Anisa Su
Prepatory patch for following FMAPI Add/Release Patches. Refactors part
of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
function to create DC Event Records and insert in the event log.
Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
accessed b
From: Anisa Su
Add a lock on the bitmap of each CXLDCRegion in preparation for the next
patch which implements FMAPI Set DC Region Configuration. This command
can modify the block size, which means the region's bitmap must be updated
accordingly.
The lock becomes necessary when commands that add
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff --git
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 of set to merge:
- Fixed blksize check in set dc region config
- Added check that it is a power of 2 (and host-ut
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw/mem
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 for merge:
- Added a missing : in a comment similar to Fan
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 106 +
1 file changed, 106 insertions(+)
diff --gi
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_events.h | 15 +++
hw/mem/cxl_type3.c | 15 ---
2 files changed, 15 insertions(
From: Anisa Su
Add booleans to DC Region struct to represent dsmas flags (defined in CDAT) in
preparation for the next command, which returns the flags in the next mailbox
command 0x5601.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 for merge
- Added some
From: Anisa Su
FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
v2 series for merge.
- Modify the code that fills in the support blk sizes to not
do effectively 2**log2(x) when we
From: Fan Ni
Per cxl r3.2 Section 9.13.3.3, extent capacity tracking should include
extents in different states including added, pending, etc.
Before the change, for the in-device extent number tracking purpose, we only
have "total_extent_count" defined, which only tracks the number of
extents a
v2:
- Missing colon and tags (Fan)
- Simpler handling block size parameters. The spec constrains these to
be power of 2 so the v1 code of BITUL((int)log2(x) is equivalent of
just using x directly. (Michael)
- Check for power of 2 (Fan + Anisa)
Hi Michael,
I consider these ready for upstream
On Mon, 14 Jul 2025 17:21:10 +
Anisa Su wrote:
> On Mon, Jul 14, 2025 at 06:02:26PM +0100, Jonathan Cameron wrote:
> > On Mon, 14 Jul 2025 09:45:31 -0700
> > Fan Ni wrote:
> >
> > > On Mon, Jul 14, 2025 at 03:16:38PM +0100, Jonathan Cameron wrote:
> > > > On Mon, 14 Jul 2025 15:15:12 +0
On Mon, 14 Jul 2025 09:45:31 -0700
Fan Ni wrote:
> On Mon, Jul 14, 2025 at 03:16:38PM +0100, Jonathan Cameron wrote:
> > On Mon, 14 Jul 2025 15:15:12 +0100
> > Jonathan Cameron wrote:
> >
> > > On Mon, 14 Jul 2025 15:02:18 +0100
> > > Jonathan Cameron wrote:
> > >
> > > > On Mon, 14 Jul 2
On Mon, 14 Jul 2025 11:57:19 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Jul 14, 2025 at 03:10:41PM +0100, Alireza Sanaee wrote:
> > On Mon, 14 Jul 2025 09:09:10 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, Jun 04, 2025 at 12:52:32PM +0100, Alireza Sanaee wrote:
> > > > From: Yic
On Mon, 14 Jul 2025 15:02:18 +0100
Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 05:32:19 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > > From: Anisa Su
> > >
> > > FM DCD Management command 0x5602 implemented per CXL r3.2 Sp
On Mon, 14 Jul 2025 15:15:12 +0100
Jonathan Cameron wrote:
> On Mon, 14 Jul 2025 15:02:18 +0100
> Jonathan Cameron wrote:
>
> > On Mon, 14 Jul 2025 05:32:19 -0400
> > "Michael S. Tsirkin" wrote:
> >
> > > On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > > > From: An
On Mon, 14 Jul 2025 05:32:19 -0400
"Michael S. Tsirkin" wrote:
> On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.3
> >
> > Reviewed-by: Fan Ni
> > Signed-off-by: An
On Thu, 3 Jul 2025 16:23:57 +
Fan Ni wrote:
> On Wed, Jul 02, 2025 at 05:02:16PM +0100, Jonathan Cameron wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by: Anisa Su
> > Signed-off-by: Jonathan Came
On Thu, 3 Jul 2025 14:35:36 +0200
Eric Auger wrote:
> The disassembled DSDT table is given below.
I think the aim for this one should be to highlight the blobs where it differs
from the previous rather than having the whole thing.
>
> /*
> * Intel ACPI Component Architecture
> * AML/ASL+ Di
On Thu, 3 Jul 2025 14:35:35 +0200
Eric Auger wrote:
> The disassembled DSDT table is given below
I'd suggest maybe a spot of cropping to bring this down to a reasonable length.
See inline.
Otherwise LGTM
Reviewed-by: Jonathan Cameron
>
> * Original Table Header:
> * Signature
On Thu, 3 Jul 2025 14:35:32 +0200
Eric Auger wrote:
> Set up the IO registers used to communicate between QEMU
> and ACPI.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Thu, 3 Jul 2025 14:35:28 +0200
Eric Auger wrote:
> QEMU will notify the OS about PCI hotplug/hotunplug events through
> GED interrupts. Let the GED device handle a new PCI hotplug event.
> On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK
> mutex held.
>
> The GED device us
On Thu, 3 Jul 2025 14:35:22 +0200
Eric Auger wrote:
> Changes relate to the introduction of pieces related to
> acpi-index static support along with root ports with no hotplug.
>
> +
> +Scope (\_SB.PCI0)
> +{
> +Method (EDSM, 5, Serialized)
> +{
> +If
On Thu, 3 Jul 2025 14:35:19 +0200
Eric Auger wrote:
> Use a specific DSDT.viot reference blob instead of relying on
> the default DSDT blob. The context has not changed.
So this is the same as the default until the next patch?
Maybe should introduce the file only then instead.
Not important th
On Thu, 3 Jul 2025 14:35:17 +0200
Eric Auger wrote:
> The test misses a variant and this puts the mess on subsequent
> rebuild-expected-aml.sh where a first DSDT reference blob is
> overriden by another one.
>
> Signed-off-by: Eric Auger
For completeness..
Reviewed-by: Jonathan Cameron
On Thu, 3 Jul 2025 14:35:18 +0200
Eric Auger wrote:
> Signed-off-by: Eric Auger
The wide range of ways setting variant up is coded in this file is
a bit more creative than I'd like and makes it hard to spot if there
are other cases of this. I 'think' this is only one other than
base tests tha
On Thu, 3 Jul 2025 10:16:50 +0100
wrote:
> From: Shiju Jose
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in
Add a single complex case for aarch64 virt machine.
Given existing much more comprehensive tests for x86 cover the common
functionality, a single test should be enough to verify that the aarch64
part continues to work.
Tested-by: Itaru Kitayama
Reviewed-by: Eric Auger
Signed-off-by: Jonathan Ca
Only add one very simple example as all the i386/pc examples will work
for arm/virt with a change to appropriate executable and appropriate
standard launch line for arm/virt. Note that max cpu is used to
ensure we have plenty of physical address space.
Suggested-by: Peter Maydell
Reviewed-by: Eri
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap. This is a hole in the current
map so adding them here has no impact on placement of other memory regions
(tested with enough CPUs for GIC_REDIST2 to be
Previously these somewhat device like structures were tracked using a list
in the CXLState in each machine. This is proving restrictive in a few
cases where we need to iterate through these without being aware of the
machine type. Just make them sysbus devices.
Restrict them to not user created as
To enable these to be found in a fixed order, that order needs to be known.
This will later be used to sort a list of these structures so that address
map and ACPI table entries are predictable.
Tested-by: Li Zhijian
Reviewed-by: Li Zhijian
Reviewed-by: Fan Ni
Reviewed-by: Eric Auger
Signed-of
v17: Thanks to Eric for review
- Add a comment to the high memory map to reduce the chance of nasty
surprises in the future as similar to device_memory, the CXL
Fixed Memory Windows are of variable size as so can't be represented
by explicit entries in the map.
- Updated a couple of patch des
On Thu, 3 Jul 2025 09:46:32 +0100
Shameer Kolothum wrote:
> Commit d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables
> when its=off") moved ITS group node generation under the its=on condition.
> However, it still creates rc_its_idmaps unconditionally, which results in
> duplic
On Thu, 3 Jul 2025 04:17:28 +
Fan Ni wrote:
> On Thu, Jun 26, 2025 at 10:23:32PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by: Anisa Su
> > ---
>
> Minor commen
On Thu, 3 Jul 2025 04:21:25 +
Fan Ni wrote:
> On Thu, Jun 26, 2025 at 10:23:33PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.6
> >
> > Signed-off-by: Anisa Su
> > ---
> Minor comments
From: Anisa Su
FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section 7.6.7.6.6
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 88 ++
1 file changed, 88 insertions(+)
diff --git a/hw/cxl/cxl-mailbox
From: Anisa Su
Prepatory patch for following FMAPI Add/Release Patches. Refactors part
of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
function to create DC Event Records and insert in the event log.
Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
accessed b
From: Anisa Su
FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section 7.6.7.6.5
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 4 ++
hw/cxl/cxl-mailbox-utils.c | 109
hw/mem/cxl_type3.c
From: Anisa Su
FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section 7.6.7.6.3
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 3 ++
include/hw/cxl/cxl_mailbox.h | 6 +++
hw/cxl/cxl-mailbox-utils.c | 86 +
From: Anisa Su
FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section 7.6.7.6.4
Very similar to previously implemented command 0x4801.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 76 +
From: Anisa Su
Add a lock on the bitmap of each CXLDCRegion in preparation for the next
patch which implements FMAPI Set DC Region Configuration. This command
can modify the block size, which means the region's bitmap must be updated
accordingly.
The lock becomes necessary when commands that add
From: Anisa Su
Move definition/enum to cxl_events.h for shared use in next patch
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_events.h | 15 +++
hw/mem/cxl_type3.c | 15 ---
2 files changed, 15 insertions(
From: Anisa Su
FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section 7.6.7.6.2
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 106 +
1 file changed, 106 insertions(+)
diff --gi
From: Anisa Su
FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section 7.6.7.6.1.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_device.h | 1 +
hw/cxl/cxl-mailbox-utils.c | 59 +
hw/mem/c
From: Anisa Su
Add booleans to DC Region struct to represent dsmas flags (defined in CDAT) in
preparation for the next command, which returns the flags in the next mailbox
command 0x5601.
Reviewed-by: Fan Ni
Signed-off-by: Anisa Su
Signed-off-by: Jonathan Cameron
---
include/hw/cxl/cxl_devic
Hi Michael,
I consider these ready for upstream. They are only lightly tweaked from
Anisa's last posting to drop some long lines and change a few patch
titles + drag them to be directly based on upstream rather than on top
of some stuff on my gitlab tree (trivial fuzz + context stuff only in
the
From: Fan Ni
Per cxl r3.2 Section 9.13.3.3, extent capacity tracking should include
extents in different states including added, pending, etc.
Before the change, for the in-device extent number tracking purpose, we only
have "total_extent_count" defined, which only tracks the number of
extents a
On Tue, 1 Jul 2025 18:12:39 +0200
Eric Auger wrote:
> Hi Jonathan,
> On 7/1/25 5:52 PM, Jonathan Cameron wrote:
> > On Tue, 1 Jul 2025 17:34:36 +0200
> > Eric Auger wrote:
> >
> >> Hi Jonathan,
> >>
> >> On 6/25/25 6:19 PM, Jonathan Cameron
On Tue, 1 Jul 2025 17:34:36 +0200
Eric Auger wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extende
On Tue, 1 Jul 2025 15:26:26 +0200
Eric Auger wrote:
> Hi Jonathan,
>
> On 6/25/25 6:19 PM, Jonathan Cameron via wrote:
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extende
On Fri, 27 Jun 2025 16:38:16 +
Anisa Su wrote:
> On Fri, Jun 27, 2025 at 10:48:59AM +0100, Jonathan Cameron wrote:
> > On Thu, 26 Jun 2025 23:41:15 +
> > anisa.su...@gmail.com wrote:
> >
> > > From: Anisa Su
> > >
> > > Per the spec, FMAPI commands (0x51-0x59) must be bound with
> >
On Thu, 26 Jun 2025 22:23:33 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
A few more long line related tweaks.
> ---
> hw/cxl/cxl-mailbox-utils.c | 79 ++
On Thu, 26 Jun 2025 22:23:32 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
There are a few long lines in here check patch doesn't like.
I tweaked as described inline whilst picking them up.
>
> Si
On Thu, 26 Jun 2025 22:23:26 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section
> 7.6.7.6.2
>
> Reviewed-by: Fan Ni
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 103
On Fri, 27 Jun 2025 11:55:20 +0200
Eric Auger wrote:
> From: Gustavo Romero
>
> Add 2 new tests:
> - test_acpi_aarch64_virt_acpi_pci_hotplug tests the acpi pci hotplug
> using -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
> - test_acpi_aarch64_virt_pcie_root_port_hpoff tests static
On Fri, 27 Jun 2025 11:55:19 +0200
Eric Auger wrote:
> From: Gustavo Romero
>
> Soon we will introduce new tests related to ACPI PCI hotplug and
> acpi-index that will use a new reference blob:
>
> tests/data/acpi/aarch64/virt/DSDT.acpipcihp
> tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex
>
On Fri, 27 Jun 2025 11:55:18 +0200
Eric Auger wrote:
> Set up the IO registers used to communicate between QEMU
> and ACPI.
>
> Signed-off-by: Eric Auger
Follow on comment inline. Otherwise LGTM
Reviewed-by: Jonathan Cameron
>
> ---
> v2 -> v3:
> - remove acpi_ged_state->pcihp_state.use_ac
On Fri, 27 Jun 2025 11:55:17 +0200
Eric Auger wrote:
> Use a local SysBusDevice handle. Also use the newly introduced
> sysbus_mmio_map_name which brings better readability about the region
> being mapped. GED device has regions which exist depending on some
> external properties and it becomes d
On Fri, 27 Jun 2025 11:55:14 +0200
Eric Auger wrote:
> QEMU will notify the OS about PCI hotplug/hotunplug events through
> GED interrupts. Let the GED device handle a new PCI hotplug event.
> On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK
> mutex held.
>
> The GED device us
On Fri, 27 Jun 2025 11:55:15 +0200
Eric Auger wrote:
> Add a subsection to migrate the AcpiPciHpState state.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 11:55:13 +0200
Eric Auger wrote:
> Let pass the root bus to ich9 and piix4 through a property link
> instead of through an argument passed to acpi_pcihp_init().
>
> Also make sure the root bus is set at the entry of acpi_pcihp_init().
>
> The rationale of that change is to b
On Fri, 27 Jun 2025 11:55:09 +0200
Eric Auger wrote:
> Modify the DSDT ACPI table to enable ACPI PCI hotplug.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 12:00:51 +0200
Eric Auger wrote:
> Hi,
>
> On 6/27/25 11:55 AM, Eric Auger wrote:
> > Changes relate to the introduction of pieces related to
> > acpi-index static support along with root ports with no hotplug.
> >
> > +
> > +Scope (\_SB.PCI0)
> > +{
> > +Meth
On Fri, 27 Jun 2025 11:55:07 +0200
Eric Auger wrote:
> hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index
>
> Add the requested ACPI bits requested to support static acpi-index
> for non hotplug ports.
>
> Signed-off-by: Eric Auger
Matches up with the i386 code so LGTM
Rev
On Fri, 27 Jun 2025 11:55:06 +0200
Eric Auger wrote:
> From: Gustavo Romero
>
> This commit adds DSDT blobs to the whilelist in the prospect to
> allow changes in the arm virt DSDT method.
>
> Signed-off-by: Gustavo Romero
> Signed-off-by: Eric Auger
>
Always feels slightly silly to give ta
On Fri, 27 Jun 2025 11:55:05 +0200
Eric Auger wrote:
> Move aml_pci_edsm to pci-bridge.c since we want to reuse that for
> ARM and acpi-index support. Also rename it into build_pci_bridge_edsm.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On Fri, 27 Jun 2025 11:54:59 +0200
Eric Auger wrote:
> Update the reference DSDT blobs after GPEX _OSC change. The _OSC change
> affects the aarch64 'virt' and the x86 'microvm' machines.
>
> DSDT diff is the same for all the machines/tests:
>
> * Original Table Header:
> * Signature
On Fri, 27 Jun 2025 11:54:58 +0200
Eric Auger wrote:
> gpex build_host_bridge_osc() and x86 originated
> build_pci_host_bridge_osc_method() are mostly identical.
>
> In GPEX, SUPP is set to CDW2 but is not further used. CTRL
> is same as Local0.
>
> So let gpex code reuse build_pci_host_bridge_
On Fri, 27 Jun 2025 11:54:56 +0200
Eric Auger wrote:
> Retrieve the acpi pcihp property value from the ged. In case this latter
> is not set, PCI native hotplug is used on pci0. For expander bridges we
> keep pci native hotplug, as done on x86 q35.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jo
On Thu, 26 Jun 2025 23:41:15 +
anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Per the spec, FMAPI commands (0x51-0x59) must be bound with
> MCTP_MT_CXL_FMAPI. Fix the conditions ensuring this in i2c_mctp_cxl.c
> and dev-mctp.c
>
> Move the opcode enum from cxl-mailbox-utils.c to cxl_mail
Only add one very simple example as all the i386/pc examples will work
for arm/virt with a change to appropriate executable and appropriate
standard launch line for arm/virt. Note that max cpu is used to
ensure we have plenty of physical address space.
Suggested-by: Peter Maydell
Signed-off-by: J
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap. This is a hole in the current
map so adding them here has no impact on placement of other memory regions
(tested with enough CPUs for GIC_REDIST2 to be
Add a single complex case for aarch64 virt machine.
Given existing much more comprehensive tests for x86 cover the
common functionality, a single test should be enough to verify
that the aarch64 part continue to work.
Tested-by: Itaru Kitayama
Signed-off-by: Jonathan Cameron
---
v16: Update to
Previously these somewhat device like structures were tracked using a list
in the CXLState in each machine. This is proving restrictive in a few
cases where we need to iterate through these without being aware of the
machine type. Just make them sysbus devices.
Restrict them to not user created as
To enable these to be found in a fixed order, that order needs to be known.
This will later be used to sort a list of these structures so that address
map and ACPI table entries are predictable.
Tested-by: Li Zhijian
Reviewed-by: Li Zhijian
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
v16:
- Mostly additional documentation and descriptive text in
patch titles.
- Update test to reflect changes to other tests.
- Update physmem_max in virt to include the CXL memory.
Updated cover letter
Back in 2022, this series stalled on the absence of a solution to device
tree support for PC
On Fri, 13 Jun 2025 18:21:25 +0100
Jonathan Cameron wrote:
> On Fri, 13 Jun 2025 17:07:24 +0100
> Peter Maydell wrote:
>
> > On Fri, 13 Jun 2025 at 16:20, Jonathan Cameron
> > wrote:
> > >
> > > On Fri, 13 Jun 2025 13:57:39 +0100
> > > Peter Maydell wrote:
> > >
> > > > On Thu, 12 Jun 2
On Tue, 17 Jun 2025 14:48:32 -0700
Davidlohr Bueso wrote:
> The current check incorrectly misses the 0% case, which semantically
> can either be not running or one that just started. The runtime
> is a better way to check for 0%, 100% or aborted. This is currently
> benign in the kernel equivalen
On Mon, 23 Jun 2025 10:42:30 +0100
Shameer Kolothum wrote:
> For the legacy smmuv3 test case, IORT has a single SMMUV3 node and
> a Root Complex node with three ID mappings of which two points to
> the SMMUv3 node and the remaining one points to ITS.
I haven't checked the blobs line by line but l
On Mon, 23 Jun 2025 10:42:29 +0100
Shameer Kolothum wrote:
> For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
> one of which has bypass_iommu enabled. The generated IORT table contains
> a single SMMUv3 node and a Root Complex node with three ID mappings. Two
> of these I
On Mon, 23 Jun 2025 10:42:28 +0100
Shameer Kolothum wrote:
> The tests to be added exercises both legacy(iommu=smmuv3) and new
> -device arm-smmuv3,.. cases.
>
> Signed-off-by: Shameer Kolothum
Reviewed-by: Jonathan Cameron
On Mon, 23 Jun 2025 10:42:27 +0100
Shameer Kolothum wrote:
> Now that arm,virt can have user-creatable smmuv3 devices, document it.
>
> Signed-off-by: Shameer Kolothum
Reviewed-by: Jonathan Cameron
> ---
> qemu-options.hx | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/qemu-
On Mon, 23 Jun 2025 10:42:26 +0100
Shameer Kolothum wrote:
> Allow cold-plugging of an SMMUv3 device on the virt machine when no
> global (legacy) SMMUv3 is present or when a virtio-iommu is specified.
>
> This user-created SMMUv3 device is tied to a specific PCI bus provided
> by the user, so e
On Mon, 23 Jun 2025 10:42:25 +0100
Shameer Kolothum wrote:
> Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus.
> However, when retrieving IOMMU ops for a device using
> pci_device_get_iommu_bus_devfn(), the function checks the parent_dev
> and fetches IOMMU ops from the parent
On Mon, 23 Jun 2025 10:42:24 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> This is useful as the subsequent support for new SMMUv3 dev will also
> use the same.
>
> Signed-off-by: Nicolin Chen
> Reviewed-by: Donald Dutile
> Reviewed-by: Eric Auger
> Tested-by: Nathan Chen
> Signed
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