[PATCH v2 03/12] hw/riscv/virt: Use setprop_sized_cells for memory

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw

[PATCH v2 12/12] hw/riscv/virt: Use setprop_sized_cells for pcie

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67490c5c693a..47e573f85ab1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -894,8 +894,8

[PATCH v2 10/12] hw/riscv/virt: Use setprop_sized_cells for rtc

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 7c38a9048044..4fa2bad24804 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -992,8 +992,9

[PATCH v2 07/12] hw/riscv/virt: Use setprop_sized_cells for virtio

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67e60eec1f00..851c7cc82ad5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -856,9 +856,7

[PATCH v2 06/12] hw/riscv/virt: Use setprop_sized_cells for plic

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fd966a34277..67e60eec1f00 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -493,8 +493,8

[PATCH v2 05/12] hw/riscv/virt: Use setprop_sized_cells for aclint

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 205fa6e44f29..4fd966a34277 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c

[PATCH v2 02/12] hw/riscv/virt: Use setprop_sized_cells for clint

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 875eb7155a30..5143a46a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -346,8 +346,8

[PATCH v2 08/12] hw/riscv/virt: Use setprop_sized_cells for reset

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 851c7cc82ad5..b59f10dabe19 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -932,8 +932,9

[PATCH v2 04/12] hw/riscv/virt: Use setprop_sized_cells for aplic

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e074a296751a..205fa6e44f29 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -655,8 +655,8

[PATCH v2 00/12] hw/riscv/virt: device tree reg cleanups

t,aia=aplic-imsic. Joel Stanley (12): hw/riscv/virt: Fix clint base address type hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Use setprop_sized_cells for memory hw/riscv/virt: Use setprop_sized_cells for aplic hw/riscv/virt: Use setprop_sized_cells for aclint hw/riscv

[PATCH v2 09/12] hw/riscv/virt: Use setprop_sized_cells for uart

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b59f10dabe19..7c38a9048044 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -966,9 +966,9

[PATCH v2 11/12] hw/riscv/virt: Use setprop_sized_cells for iommu

Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fa2bad24804..67490c5c693a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1088,8 +1088,7

[PATCH v2 01/12] hw/riscv/virt: Fix clint base address type

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv

Re: [PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

On Tue, 29 Apr 2025 at 21:56, Daniel Henrique Barboza wrote: > > > > On 4/29/25 3:12 AM, Joel Stanley wrote: > > The address is a hardware address, so use hwaddr for consistency with > > the rest of the machine. > > > > Signed-off-by: Joel Stanley > >

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

On Wed, 30 Apr 2025 at 02:41, Daniel Henrique Barboza wrote: > > > > On 4/29/25 9:40 AM, Daniel Henrique Barboza wrote: > > Joel, > > > > I'll make these changes in this patch to be consistent with what we've > > been discussing: > > > > - change addr to hwaddr > > - use HWADDR_PRIx instead of PRI

[PATCH 10/13] hw/riscv/virt: Use setprop_sized_cells for rtc

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 08/13] hw/riscv/virt: Use setprop_sized_cells for reset

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 12/13] hw/riscv/virt: Use setprop_sized_cells for pcie

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 13/13] NOMERGE: virt: Adjust devices so everything is > 4G

Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 42 +- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cd19c266e62a..1162b3a4b71a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -80,27 +80,27

[PATCH 01/13] hw/riscv/virt: Fix clint base address type

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17a790821484..e4c0ac8a2a9a 100644

[PATCH 09/13] hw/riscv/virt: Use setprop_sized_cells for uart

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 03/13] hw/riscv/virt: Use setprop_sized_cells for memory

Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 873d41d10c70..ed28bc06114a 100644

[PATCH 07/13] hw/riscv/virt: Use setprop_sized_cells for virtio

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 11/13] hw/riscv/virt: Use setprop_sized_cells for iommu

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 01/13] riscv/virt: Fix address type in create_fdt_socket_clint

The address is a hardware address, so use hwaddr for consistency with the rest of the machine. Signed-off-by: Joel Stanley --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17a790821484..e4c0ac8a2a9a 100644

[PATCH 00/13] hw/riscv/virt: device tree reg cleanups

n the existing code when the reg property describes an address > 4GB. Based-on: 20250423110630.2249904-1-dbarb...@ventanamicro.com Joel Stanley (13): hw/riscv/virt: Fix clint base address type hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Use setprop_sized_cells for memory

[PATCH 06/13] hw/riscv/virt: Use setprop_sized_cells for plic

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 02/13] hw/riscv/virt: Use setprop_sized_cells for clint

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 04/13] hw/riscv/virt: Use setprop_sized_cells for aplic

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

[PATCH 05/13] hw/riscv/virt: Use setprop_sized_cells for aclint

The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Signed-off-by: Joel Stanley

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

On Fri, 25 Apr 2025 at 22:03, Daniel Henrique Barboza wrote: > > > > On 4/24/25 6:41 AM, Joel Stanley wrote: > > On Wed, 23 Apr 2025 at 20:39, Daniel Henrique Barboza > > wrote: > >> > >> We can avoid the 'long' casts by using PRIx64 and

Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()

On Fri, 25 Apr 2025 at 21:23, Daniel Henrique Barboza wrote: > > > > On 4/24/25 6:51 AM, Joel Stanley wrote: > > On Wed, 23 Apr 2025 at 20:37, Daniel Henrique Barboza > > wrote: > >> > >> Throughout the code we're accessing the board memmap, most o

Re: [PATCH 9/9] hw/riscv: Add a network device e1000e to the boston-aia

On Fri, 25 Apr 2025 at 23:37, Djordje Todorovic wrote: > > Add a network device e1000e to the boston-aia board model. > There is no pch_gbe emulation, so we add e1000e in slot 0 func 1, > instead. We need to pass func to call pci_parse_devaddr to find > out slot and func. > > Signed-off-by: Chao-y

Re: [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef

On Mon, 28 Apr 2025 at 17:10, Paolo Bonzini wrote: I think a typo has snuck into the subject here. s/TT/Thead/ > > Reviewed-by: Alistair Francis > Signed-off-by: Paolo Bonzini > --- > target/riscv/cpu.c | 61 +- > 1 file changed, 28 insertions(+), 3

Re: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init()

ning > it to a temp variable 'memmap'. Code is copy/pasted around all the time > and being consistent is important. Reviewed-by: Joel Stanley Cheers, Joel

Re: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings

On Wed, 23 Apr 2025 at 20:39, Daniel Henrique Barboza wrote: > > We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt > strings for uint64_t and hwaddr types. > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/virt.c | 29 +++-- > 1 file chang

[PATCH-for-10.0] hw/core/machine.c: Fix -machine dumpdtb=file.dtb

on") Signed-off-by: Joel Stanley --- hw/core/machine.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index f52a4f2273b2..63c6ef93d296 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -173

Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

Hi Jamin, On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery wrote: > Thanks, I'll consider this updated diagram as well while I put my own > together from the other pieces of info you've provided. When you send the next version, please try to separate your code cleanups and minor renames into a differ

Re: [PATCH] hw/aspeed: Correct minimum access size for all models

On Mon, 18 Nov 2024 at 20:40, Peter Maydell wrote: > > On Mon, 18 Nov 2024 at 02:19, Joel Stanley wrote: > > > > Guest code was performing a byte load to the SCU MMIO region, leading to > > the guest code crashing (it should be using proper accessors, but > > tha

[PATCH] hw/aspeed: Correct minimum access size for all models

ccess size of 1. [1] See the 'ARM Address Space Mapping' table in the ASPEED docs. This is section 6.1 in the ast2400 and ast2700, and 7.1 in the ast2500 and ast2600 datasheets. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley --- hw/fsi/aspeed

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

On Wed, 23 Oct 2024 at 19:50, Jamin Lin wrote: > > > Someone (aspeed?) should take a todo to resolve the HACE situation in > > u-boot. > > > > I will build a br2 image with upstream u-boot. The ones we use for tests > > have > > an OpenBMC u-boot IIRC. > > > > I used ASPEED FORKED OpenBMC pre-bui

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

On Wed, 23 Oct 2024 at 02:35, Cédric Le Goater wrote: > > On 10/22/24 13:54, Joel Stanley wrote: > > On Wed, 16 Oct 2024 at 01:23, Jamin Lin wrote: > > > >> 3. Test HACE model with u-boot hash command > >> a. load test file to address 8300 via tftp &g

Re: [PATCH v6] hw/misc/aspeed_hace: Fix SG Accumulative hashing

On Wed, 16 Oct 2024 at 01:23, Jamin Lin wrote: > 3. Test HACE model with u-boot hash command > a. load test file to address 8300 via tftp > ast# tftp 8300 jamin_lin/32MB > b. get sha256 > ast# hash sha256 8300 200 > sha256 for 8300 ... 84ff ==> > 1ddcccdba742d762e2b8da0bc

Missing image on storage.kernelci.org

I was attempting to run some boot tests today and saw this: (11/39) tests/avocado/boot_linux_console.py:BootLinuxConsole.test_arm_bpim2u_gmac: CANCEL: Missing asset http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20221116.0/armel/rootfs.ext2.xz (5.21 s) Cheers, Joel

Re: [PATCH v2] aspeed: Deprecate the tacoma-bmc machine

On Sat, 31 Aug 2024 at 05:41, Guenter Roeck wrote: > > On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote: > > Hello, > > > > > > > > > I solved the problem by adding support for IBM Bonnell (which > > > > > instantiates > > > > > the TPM chip through its devicetree file, similar to

Re: [RFC PATCH 11/11] ppc/pnv: Change powernv default to powernv10

On Wed, 11 Oct 2023 at 07:28, Nicholas Piggin wrote: > > On Tue Oct 10, 2023 at 10:05 PM AEST, Joel Stanley wrote: > > On Tue, 10 Oct 2023 at 18:24, Nicholas Piggin wrote: > > > > > > POWER10 is the latest IBM Power machine. Although it is not offered in &g

Re: [PATCH v2] misc/pca9552: Let external devices set pca9552 inputs

On Fri, 6 Oct 2023 at 07:23, Glenn Miles wrote: > > Allow external devices to drive pca9552 input pins by adding > input GPIO's to the model. This allows a device to connect > its output GPIO's to the pca9552 input GPIO's. > > In order for an external device to set the state of a pca9552 > pin, t

Re: [RFC PATCH 10/11] ppc/spapr: change pseries machine default to POWER10 CPU

On Tue, 10 Oct 2023 at 18:25, Nicholas Piggin wrote: > > POWER10 is the latest pseries CPU. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley > --- > hw/ppc/spapr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/ppc/spapr

Re: [RFC PATCH 11/11] ppc/pnv: Change powernv default to powernv10

; powernv10 at the moment. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley Do we need to update the docs? We should consider updating the skiboot to the latest release too. > --- > hw/ppc/pnv.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >

Re: [RFC PATCH 05/11] testing/avocado: ppc add new BookE boot_linux_console.py tests

modern BookE images now. > > Signed-off-by: Nicholas Piggin Reviewed-by: Joel Stanley Should we get mpe to add a https://github.com/linuxppc/qemu-ci-images for you to keep those kernel images? But perhaps you'd prefer to keep them on gitlab. Just a suggestion. > --- > tes

Re: [PATCH 1/4] aspeed/i2c: Clean up local variable shadowing

; > Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley messy. > --- > hw/i2c/aspeed_i2c.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c > index 7275d40749a9..1037c22b2f79 100644 > --- a/hw/i2c/a

Re: [Qemu-devel] [PATCH 08/19] aspeed/timer: Fix behaviour running Linux

On Fri, 22 Sept 2023 at 13:21, Cédric Le Goater wrote: > > +t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > > +return calculate_time(t, MAX(MAX(t->match[0], t->match[1]), 0)); > > This MAX(MAX(x, y), 0) looks strange to me. Would you remember where it comes > from ? Thanks, That look

Re: [PATCH v3.2 5/7] aspeed: Create flash devices only when defaults are enabled

noted that in this case, the ROM will not be installed and the > initial boot sequence (U-Boot loading) will fetch instructions using > SPI transactions which is significantly slower. That's exactly how HW > operates though. > > Signed-off-by: Cédric Le Goater Reviewe

Re: [PATCH v3 5/7] aspeed: Create flash devices only when defaults are enabled

On Thu, 31 Aug 2023 at 13:22, Cédric Le Goater wrote: > > On 8/31/23 15:00, Joel Stanley wrote: > > On Thu, 31 Aug 2023 at 12:39, Cédric Le Goater wrote: > >> > >> When the -nodefaults option is set, flash devices should be created > >> with : > >>

Re: [PATCH v3 5/7] aspeed: Create flash devices only when defaults are enabled

the first foray for the aspeed machines into nodefaults removing things that previously would have just worked. I know we haven't had it in our recommended command lines for a long time, so that's fine. Reviewed-by: Joel Stanley Should the content of your commit message go in the docs? &g

Re: [PATCH for-8.2 2/3] pnv/lpc: Hook up xscom region for P9/P10

On Tue, 29 Aug 2023 at 14:45, Cédric Le Goater wrote: > > On 8/9/23 16:56, Frederic Barrat wrote: > > Hello Joel, > > > > So we're re-using the same xscom ops as on P8. A quick look at the > > definition of those 4 registers on P8 (0xb0020) and on P9/P10 (0x00090040) > > seem to show they are no

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

re any value in testing both the old and the new images? Reviewed-by: Joel Stanley > > Signed-off-by: Cédric Le Goater > --- > > Requires patches from Hang Yu [1] > > [1] > https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/ >

Re: [PATCH v1 5/7] hw/fsi: IBM's On-chip Peripheral Bus

PEED SoC due > to tight integration of the FSI master IP with the OPB, mainly the > existence of an MMIO-mapping of the CFAM address straight onto a > sub-region of the OPB address space. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Cédric Le Goater > Signed-off-b

Re: [PATCH v1 4/7] hw/fsi: Introduce IBM's FSI

a CFAM. > > Signed-off-by: Andrew Jeffery > Signed-off-by: Cédric Le Goater > Signed-off-by: Ninad Palsule Reviewed-by: Joel Stanley > --- > hw/fsi/cfam.c | 1 + > hw/fsi/fsi-master.c | 203 > hw/fsi/fsi.c

Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > An APB-to-OPB bridge enabling access to the OPB from the ARM core in > the AST2600. Hardware limitations prevent the OPB from being directly > mapped into A

Re: [PATCH v1 7/7] hw/arm: Hook up FSI module in AST2600

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule wrote: > > This patchset introduces IBM's Flexible Service Interface(FSI). > > Time for some fun with inter-processor buses. FSI allows a service > processor access to the internal buses of a host POWER processor to > perform configuration or debugging.

Re: [PATCH v1 1/7] hw/fsi: Introduce IBM's Local bus

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule wrote: > > This is a part of patchset where IBM's Flexible Service Interface is > introduced. > > The LBUS is modelled to maintain the qdev bus hierarchy and to take > advantage of the object model to automatically generate the CFAM > configuration block

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

Hi Ninad, On Fri, 25 Aug 2023 at 20:51, Ninad Palsule wrote: > > Hello, > > Please review the patch-set. > > This is a first step towards introducing model for IBM's Flexible > Service Interface. The full functionality will be implemented over the > time. You have a typo in the subject, I think

[PATCH for-8.2 3/3] HACK: pnv/lpc: Set up XSCOM dt for P9

t(lpc); lpc->chip_id = gcid; - lpc->mbase = (void *)addr; + lpc->xbase = dt_get_address(lpc_node, 0, NULL); lpc->fw_idsel = 0xff; lpc->fw_rdsz = 0xff; lpc->node = lpc_node; Signed-off-by: Joel Stanley --- hw/ppc/pnv_lpc.c | 5 +

[PATCH for-8.2 1/3] pnv/lpc: Place mmio regs in their own memory region

The P9 and P10 models re-used the xscom_regs memory region for the mmio access, which is confusing. Add a separate memory region in preparation for enabling both xscom and mmio access. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_lpc.h | 3 ++- hw/ppc/pnv.c | 4 ++-- hw/ppc

[PATCH for-8.2 2/3] pnv/lpc: Hook up xscom region for P9/P10

>From P9 on the LPC bus is memory mapped. However the xscom access still is possible, so add it too. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 4 hw/ppc/pnv_lpc.c | 6 ++ 3 files changed, 16 insertions(+) diff --gi

[PATCH for-8.2 0/3] pnv/lpc: Hook up xscoms for LPC

not be applied. Joel Stanley (3): pnv/lpc: Place mmio regs in their own memory region pnv/lpc: Hook up xscom region for P9/P10 HACK: pnv/lpc: Set up XSCOM dt for P9 include/hw/ppc/pnv_lpc.h | 3 ++- include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 8 ++-- hw/ppc

[PATCH] configure: Fix linux-user host detection for ppc64le

Revert the changes in the recent "Fix linux-user host detection for riscv64" patch as it broke ppc64le. Instead add riscv to the switch statement that performs normalisation of the host cpu name. Fixes: 89e5b7935e92 ("configure: Fix linux-user host detection for riscv64")

Re: [PATCH] configure: Fix linux-user host detection for riscv64

On Sat, 5 Aug 2023 at 18:02, Richard Henderson wrote: > > Mirror the host_arch variable from meson.build, so that we > probe for the correct linux-user/include/host/ directory. This broke all of the linux-user targets for me on a ppc64le host. None show up when running configure --help, and tryin

Re: [PATCH v7 00/14] linux-user: brk fixes

On Thu, 3 Aug 2023 at 13:55, Helge Deller wrote: > > 143551 brk(NULL) = 0x0009b000 > > 143551 brk(0x0009b8fc) = 0x0009b000 > > I think the problem is the brk with 9b000 here. > It's not 64k aligned (=pages size of your ppc64le). > > Please try with this patch on top of Richard's series: > > > @@ -

Re: [PATCH v7 00/14] linux-user: brk fixes

Hi Richard, On Thu, 3 Aug 2023 at 01:53, Richard Henderson wrote: > > Builds on Helge's v6, incorporating my feedback plus > some other minor cleanup. This succeeds for the armhf static binary on ppc64le host that was previously segfaulting. However, the arm static binary on ppc64le host now se

Re: [PATCH v6 0/8] linux-user: brk fixes

On Tue, 1 Aug 2023 at 23:28, Helge Deller wrote: > > This patch series is a fix-up for some current problems > regarding heap memory / brk handling in qemu which happens > on some 32-bit platforms, e.g. problems loading static > binaries. > > This series includes the 5 patches from Akihiko Odaki >

Re: [PATCH 0/5] linux-user: brk/mmap fixes

On Mon, 31 Jul 2023 at 18:24, Helge Deller wrote: > > I re-read the thread again. As it seems Joel already tried the latest > > version from me? Sadly I can't test myself on ppc64le (static binary > > needs klibc-PupSAGgtpafMlSLXOLgje1kXFo8.so in /usr/lib which I can't > > install on a debian por

Re: [PATCH 0/5] linux-user: brk/mmap fixes

y Helge Deller, have you seen it? > ("linux-user: Fix and optimize target memory layout", a v5 already). Applying this series fixes the qemu-arm running the static armhf binary on my ppc64le host that I reported here[1]. Tested-by: Joel Stanley The changes conflict with Helge's

Re: [PATCH v5 0/3] linux-user: Fix and optimize target memory layout

On Fri, 28 Jul 2023 at 18:58, Helge Deller wrote: > > While trying to fix a bug which prevents running a static > armhf binary with linux-user, I noticed a whole bunch of > memory layout issues on various platforms. Most noteably > the free heap space was very limited in the current setup. > A lar

Re: [PATCH] gdbstub: Fix client Ctrl-C handling

On Sun, 30 Jul 2023 at 09:43, Nicholas Piggin wrote: > > On Wed Jul 26, 2023 at 4:35 PM AEST, Joel Stanley wrote: > > On Wed, 12 Jul 2023 at 02:12, Nicholas Piggin wrote: > > > > > > On Tue Jul 11, 2023 at 9:03 PM AEST, Matheus Tavares Bernardino wrote: &g

Re: [PATCH] gdbstub: Fix client Ctrl-C handling

On Wed, 12 Jul 2023 at 02:12, Nicholas Piggin wrote: > > On Tue Jul 11, 2023 at 9:03 PM AEST, Matheus Tavares Bernardino wrote: > > > Nicholas Piggin wrote: > > > > > > diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c > > > index 6911b73c07..ce8b42eb15 100644 > > > --- a/gdbstub/gdbstub.c > > >

[PATCH] ppc: Add stub implementation of TRIG SPRs

Linux sets these to control cache flush behaviour on Power9. Supervisor and hypervisor are allowed to write, and reads are noops. Add implementations to avoid noisy messages when booting Linux under the pseries machine with guest_errors enabled. Reviewed-by: Nicholas Piggin Signed-off-by: Joel

Re: [PATCH v2] ppc/pnv: Add QME region for P10

On Sat, 8 Jul 2023 at 01:17, Nicholas Piggin wrote: > > --- a/include/hw/ppc/pnv_xscom.h > > +++ b/include/hw/ppc/pnv_xscom.h > > @@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass { > > #define PNV10_XSCOM_EC(proc)\ > > ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) > > >

Re: [PATCH v2] ppc/pnv: Add QME region for P10

On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater wrote: > > On 7/7/23 09:12, Joel Stanley wrote: > > The Quad Management Engine (QME) manages power related settings for its > > quad. The xscom region is separate from the quad xscoms, therefore a new > > region is added. The

[PATCH v2] ppc/pnv: Add QME region for P10

special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley --- v2: Clean up extra whitespace Make realize quad specific so power9 doesn't end up with the qme region --- include/hw/ppc/pnv_core.h

Re: [PATCH] ppc/pnv: Add QME region for P10

On Fri, 7 Jul 2023 at 05:04, Cédric Le Goater wrote: > pnv_quad_realize realizes power9 and power10 quad objects but ... > > > } > > > > static Property pnv_quad_properties[] = { > > @@ -528,6 +581,9 @@ static void pnv_quad_power10_class_init(ObjectClass > > *oc, void *data) > > > > pq

[PATCH] ppc/pnv: Add QME region for P10

special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_core.h | 4 +++ include/hw/ppc/pnv_xscom.h | 11 hw/ppc/pnv.c | 5 hw/ppc/pnv_core.c | 56

[PATCH] ppc/pnv: Log all unimp warnings with similar message

Add the function name so there's an indication as to where the message is coming from. Change all prints to use the offset instead of the address. Signed-off-by: Joel Stanley --- Happy to use the address instead of the offset (or print both), but I like the idea of being consistent. --- h

Re: [PATCH] ppc/pnv: Set P10 core xscom region size to match hardware

On Wed, 5 Jul 2023 at 10:02, Cédric Le Goater wrote: > > On 7/5/23 04:05, Joel Stanley wrote: > > On Wed, 5 Jul 2023 at 01:27, Nicholas Piggin wrote: > >> > >> The P10 core xscom memory regions overlap because the size is wrong. > >> The P10 core+L2 xscom r

Re: [PATCH] ppc/pnv: Set P10 core xscom region size to match hardware

0108108000-00010810 (prio 0, i/o): xscom-core.7: 0x8000 00010811-000108117fff (prio 0, i/o): xscom-core.6: 0x8000 00010812-000108127fff (prio 0, i/o): xscom-core.5: 0x8000 00010814-000108147fff (prio 0, i/o): xscom-core.4: 0x8000 Reviewed-by

[PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks

Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- v2: Add scom region size to class --- include/hw/ppc/pnv_core.h | 13 - hw/ppc/pnv.c | 11

[PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific

Rename the functions to include P9 in the name in preparation for adding P10 versions. Correct the unimp read message while we're changing the function. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- v2: Fix unimp print, and grammar in the commit message --- hw/ppc/pnv_c

[PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10

27;s r-b, fixes the s/write/read/ mistakes, and is checkpatch clean. v1: https://lore.kernel.org/qemu-devel/20230630035547.80329-1-j...@jms.id.au/ Joel Stanley (5): ppc/pnv: quad xscom callbacks are P9 specific ppc/pnv: Subclass quad xscom callbacks ppc/pnv: Add P10 quad xscom model ppc/pn

[PATCH v2 4/5] ppc/pnv: Add P10 core xscom model

Like the quad xscoms, add a core model for P10 to allow future differentiation from P9. Signed-off-by: Joel Stanley --- hw/ppc/pnv_core.c | 44 ++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index

[PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom

Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger, report the core thread state is 0. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- hw/ppc/pnv_core.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/h

[PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model

(prio 0, i/o): xscom-core.0 Signed-off-by: Joel Stanley --- v2: Fix unimp read message Wrap lines at 80 col Set size --- include/hw/ppc/pnv_xscom.h | 2 +- hw/ppc/pnv.c | 2 +- hw/ppc/pnv_core.c | 54 ++ 3 files changed, 56

Re: [RFC PATCH 1/3] target/ppc: Add LPAR-per-core vs per-thread mode flag

ernv > machine, it is preferable to emulate OPAL LPAR-per-thread, so to > account for this difference a flag is added and SPRs may become either > per-thread, per-core shared, or per-LPAR shared. Per-LPAR registers > become either per-thread or per-core shared depending on the mode. > &g

Re: [PATCH 3/4] ppc/pnv: Add P10 quad ops

On Fri, 30 Jun 2023 at 07:30, Frederic Barrat wrote: > > > > On 30/06/2023 05:55, Joel Stanley wrote: > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > > index b9a57463aec4..7fff2fd9e298 100644 > > --- a/hw/ppc/pnv_core.c > > +++ b/hw/p

[PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks

Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Signed-off-by: Joel Stanley --- include/hw/ppc/pnv_core.h | 12 +++- hw/ppc/pnv.c | 11 +++ hw/ppc/pnv_core.c | 36

[PATCH 0/4] ppc/pnv: Extend "quad" model for p10

hould the model instead wired so one is created for each chiplet? Or should we report the value for all possible cores, like the P9 code does for P9X_EX_NCU_SPEC_BAR? switch (offset) { case P9X_EX_NCU_SPEC_BAR: case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ Joel Stanley (4): ppc/

[PATCH 4/4] ppc/pnv: Return zero for core thread state xscom

Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger report the core thread state is 0. Signed-off-by: Joel Stanley --- hw/ppc/pnv_core.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c

[PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific

Rename the to include P9 in the name in preparation for adding P10 versions. Signed-off-by: Joel Stanley --- hw/ppc/pnv_core.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 0bc3ad41c81c..0b1c3cccfebc 100644

[PATCH 3/4] ppc/pnv: Add P10 quad ops

Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. Signed-off-by: Joel Stanley --- hw/ppc/pnv.c | 2 +- hw/ppc/pnv_core.c | 53 +++ 2 files changed, 54 insertions(+), 1 deletion

Re: [PATCH] sungem: Add WOL MMIO

f-by: Nicholas Piggin Reviewed-by: Joel Stanley > --- > This fixes the failed MMIO error in the Linux sungem driver reset > when it clears the WOL CSR. > > Thanks, > Nick > > hw/net/sungem.c | 52 + > hw/net/trace-events | 2

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