Re: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE

Hi Radim, Does your patchset want to resolve the same issue as my sstc patch [1]? My sstc patchset has been merged to "riscv-to-apply.next". Maybe you can review it or check if there is still any issue in the "riscv-to-apply.next" branch, thanks! [1] "[PATCH v3 4/4] target/riscv: Enable/Disable

Re: [PATCH v2] target/riscv: support atomic instruction fetch (Ziccif)

Hi, Gentle ping on this patch. Thanks, Jim Shu On Thu, May 8, 2025 at 5:48 PM Jim Shu wrote: > > Support 4-byte atomic instruction fetch when instruction is natural > aligned. > > Current implementation is not atomic because it loads instruction twice > for first and last

[PATCH v3 3/4] target/riscv: Fix VSTIP bit in sstc extension.

VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will revert it's defined behavior as if sstc extension is not implemented. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/csr.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --

[PATCH v3 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

c ch19.2.1. Virtual Supervisor Timer (vstimecmp) Register A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the hip register, whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp Signed-off-by: Jim Shu Acked-by:

[PATCH v3 1/4] target/riscv: Add the checking into stimecmp write function.

Preparation commit to let aclint timer to use stimecmp write function. Aclint timer doesn't call sstc() predicate so we need to check inside the stimecmp write function. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/time_helper.c | 19 +-- 1 file ch

[PATCH v3 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/csr.c | 46 ++ target/riscv/time_helper.c | 46

[PATCH v3 0/4] Several sstc extension fixes

, which should update the timer and IRQ pending bits. Changed in v3: - Rebase to riscv-to-apply.next Changed in v2: - Remove duplicated code in riscv_timer_stce_changed() function - Add sstc spec description in the commit log Jim Shu (4): target/riscv: Add the checking into stimecmp write

[PATCH v2] target/riscv: support atomic instruction fetch (Ziccif)

mmit depends on the atomic read support of translator_ld in the commit 6a9dfe1984b0c593fb0ddb52d4e70832e6201dd6. Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/translate.c | 46 +--- 1 file changed, 34 insertions(+), 12 deletions(-) diff --g

Re: [PATCH v2 0/4] Several sstc extension fixes

Hi, Gentle ping on this patch. Thanks, Jim On Wed, Apr 9, 2025 at 10:58 AM Jim Shu wrote: > > Sorry, I forgot to write v2 changes in cover-letter. > > Changes in v2: > - Remove duplicated code in riscv_timer_stce_changed() function > - Add sstc spec description in the commi

[PATCH v2 15/18] hw/misc: riscv_wgchecker: Implement wgchecker slot registers

wgChecker slot is similar to PMP region. SW could program each slot to configure the permission of address range. Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 330 + hw/misc/riscv_worldguard.c | 3 + include/hw/misc/riscv_worldguard.h

[PATCH v2 03/18] accel/tcg: memory access from CPU will pass access_type to IOMMU

tion so that IOMMU could return the correct section of specified access_type. Signed-off-by: Jim Shu --- accel/tcg/cputlb.c | 17 ++--- include/exec/cputlb.h| 11 +++ include/exec/exec-all.h | 3 ++- system/physm

[PATCH v2 04/18] exec: Add RISC-V WorldGuard WID to MemTxAttrs

signal. Signed-off-by: Jim Shu --- include/exec/memattrs.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 8db1d30464..7a6866fa41 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -54,6 +54,11

[PATCH v2 05/18] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config

Add a device for RISCV WG global config, which contains the number of worlds, reset value, and trusted WID ... etc. This global config is used by both CPU WG extension and wgChecker devices. Signed-off-by: Jim Shu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[PATCH v2 14/18] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker

ansactions Signed-off-by: Jim Shu --- hw/misc/meson.build| 2 +- hw/misc/riscv_wgchecker.c | 603 + hw/misc/trace-events | 8 + include/hw/misc/riscv_worldguard.h | 63 +++ 4 files changed, 675 insertions(+), 1 deletion(-) c

[PATCH v2 11/18] target/riscv: Add WID to MemTxAttrs of CPU memory transactions

When a RISC-V HART has WG extension, their memory transactions will contain WID. Support MemTxAttrs in RISC-V target and add WID inside if a HART has WG extension. Signed-off-by: Jim Shu --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 51

[PATCH v2 09/18] target/riscv: Allow global WG config to set WG CPU callbacks

Some WG CPU functions depend on global WG config (like num-of-world), so we let the global WG config device to set callbacks of a RISC-V HART. Signed-off-by: Jim Shu --- target/riscv/cpu.h | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v2 10/18] target/riscv: Implement WorldGuard CSRs

The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs of CPUs in the higher privileged modes. The Smwg extension at least requires a RISC-V HART to have M/U-mode, and the Sswg/Smwgd extension at least requires a RISC-V HART to have M/S/U-mode. Signed-off-by: Jim Shu --- target

[PATCH v2 02/18] system/physmem: Remove the assertion of page-aligned section number

The physical section number is no longer ORed into the IOTLB entries together with a page-aligned pointer, so it no longer needs to be page-aligned. Signed-off-by: Jim Shu --- system/physmem.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index

[PATCH v2 07/18] target/riscv: Add hard-coded CPU state of WG extension

s, we should set it by machine code. Signed-off-by: Jim Shu --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ 3 files changed, 22 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51e49e03de..ac5092

[PATCH v2 16/18] hw/misc: riscv_wgchecker: Implement correct block-access behavior

The wgChecker is configurable for whether blocked accesses: * should cause a bus error or just read return zero and write ignore * should generate the interrupt or not Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 169 +- 1 file changed, 167

[PATCH v2 18/18] hw/riscv: virt: Add WorldGuard support

* Add 'wg=on' option to enable RISC-V WorldGuard * Add wgChecker to protect several resources: DRAM, FLASH, UART. Signed-off-by: Jim Shu --- docs/system/riscv/virt.rst | 20 + hw/riscv/Kconfig | 1 + hw/riscv/virt.c

[PATCH v2 12/18] target/riscv: Expose CPU options of WorldGuard

Expose WG CPU extensions (Smwg, Sswg, Smwgd) and WG CPU configs (mwid, mwidlist). Signed-off-by: Jim Shu --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1aba6dd853..46df970fe3 100644 --- a/target/riscv/cpu.c +++ b

[PATCH v2 17/18] hw/misc: riscv_wgchecker: Check the slot settings in translate

that point. One tricky part here is that the perm of 'blocked_io_as' is the condition of deny access. For example, if wgChecker only permits RO access, the perm of 'downstream_as' will be IOMMU_RO and the perm of 'blocked_io_as' will be IOMMU_WO. Signed

[PATCH v2 13/18] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU

riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG callback to CPUs. It is used by machine code after realizing global WG device. Signed-off-by: Jim Shu --- hw/misc/riscv_worldguard.c | 87 ++ include/hw/misc/riscv_worldguard.h | 1 + 2

[PATCH v2 08/18] target/riscv: Add defines for WorldGuard CSRs

Add CSRs for 3 WG extensions: Smwg, Smwgd, and Sswg. Signed-off-by: Jim Shu --- target/riscv/cpu_bits.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a30317c617..7705c6995e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv

[PATCH v2 06/18] target/riscv: Add CPU options of WorldGuard CPU extension

We define CPU options for WG CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating WG CSRs. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv

[PATCH v2 00/18] Implements RISC-V WorldGuard extension v0.4

WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field. Jim Shu (18): accel/tcg: Store section pointer in CPUTLBEntryFull system/physmem: Remove the assertion of pag

[PATCH v2 01/18] accel/tcg: Store section pointer in CPUTLBEntryFull

nce they are only in the path of DMA access. Currently, the bug only occurs when ARM MPC device (hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access handling. Upcoming RISC-V wgChecker device is also affected by this bug. Signed-off-by: Jim Shu --- accel/tcg/cputlb.c |

Re: [PATCH 17/17] hw/riscv: virt: Add WorldGuard support

Thanks Daniel. I will fix the RST doc and typo issue in the v2 patch! Jim On Tue, Apr 15, 2025 at 9:20 PM Daniel Henrique Barboza wrote: > > > > On 4/15/25 5:12 AM, Jim Shu wrote: > > * Add 'wg=on' option to enable RISC-V WorldGuard > > * Add wgChecker to prot

Re: [PATCH 01/17] accel/tcg: Store section pointer in CPUTLBEntryFull

evich wrote: > > On 2025-04-15 10:12, Jim Shu wrote: > > 'CPUTLBEntryFull.xlat_section' stores section_index in last 12 bits to > > find the correct section when CPU access the IO region over the IOTLB > > (iotlb_to_section()). > > > > However, section_

[PATCH 06/17] target/riscv: Add hard-coded CPU state of WG extension

s, we should set it by machine code. Signed-off-by: Jim Shu --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ 3 files changed, 22 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51e49e03de..ac5092

[PATCH 05/17] target/riscv: Add CPU options of WorldGuard CPU extension

We define CPU options for WG CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating WG CSRs. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv

[PATCH 07/17] target/riscv: Add defines for WorldGuard CSRs

Add CSRs for 3 WG extensions: Smwg, Smwgd, and Sswg. Signed-off-by: Jim Shu --- target/riscv/cpu_bits.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a30317c617..7705c6995e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv

[PATCH 01/17] accel/tcg: Store section pointer in CPUTLBEntryFull

OMMU devices don't have this issue since they are only in the path of DMA access. Currently, the bug only occurs when ARM MPC device (hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access handling. Upcoming RISC-V wgChecker device is also affected by this bug.

[PATCH 12/17] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU

riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG callback to CPUs. It is used by machine code after realizing global WG device. Signed-off-by: Jim Shu --- hw/misc/riscv_worldguard.c | 87 ++ include/hw/misc/riscv_worldguard.h | 1 + 2

[PATCH 11/17] target/riscv: Expose CPU options of WorldGuard

Expose WG CPU extensions (Smwg, Sswg, Smwgd) and WG CPU configs (mwid, mwidlist). Signed-off-by: Jim Shu --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1aba6dd853..46df970fe3 100644 --- a/target/riscv/cpu.c +++ b

[PATCH 16/17] hw/misc: riscv_wgchecker: Check the slot settings in translate

that point. One tricky part here is that the perm of 'blocked_io_as' is the condition of deny access. For example, if wgChecker only permits RO access, the perm of 'downstream_as' will be IOMMU_RO and the perm of 'blocked_io_as' will be IOMMU_WO. Signed

[PATCH 00/17] Implements RISC-V WorldGuard extension v0.4

tion of HW config and CPU option of WG in the virt machine documentation - Expose CPU options of WG after WG CPU code has been implemented - Change 'mwid' and 'mwidlist' options to experimental options - Change 'world_id' to unsigned int type + bit field. Jim Shu (17

[PATCH 03/17] exec: Add RISC-V WorldGuard WID to MemTxAttrs

signal. Signed-off-by: Jim Shu --- include/exec/memattrs.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 8db1d30464..7a6866fa41 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -54,6 +54,11

[PATCH 15/17] hw/misc: riscv_wgchecker: Implement correct block-access behavior

The wgChecker is configurable for whether blocked accesses: * should cause a bus error or just read return zero and write ignore * should generate the interrupt or not Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 169 +- 1 file changed, 167

[PATCH 13/17] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker

ansactions Signed-off-by: Jim Shu --- hw/misc/meson.build| 2 +- hw/misc/riscv_wgchecker.c | 603 + hw/misc/trace-events | 8 + include/hw/misc/riscv_worldguard.h | 63 +++ 4 files changed, 675 insertions(+), 1 deletion(-) c

[PATCH 10/17] target/riscv: Add WID to MemTxAttrs of CPU memory transactions

When a RISC-V HART has WG extension, their memory transactions will contain WID. Support MemTxAttrs in RISC-V target and add WID inside if a HART has WG extension. Signed-off-by: Jim Shu --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 51

[PATCH 09/17] target/riscv: Implement WorldGuard CSRs

The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs of CPUs in the higher privileged modes. The Smwg extension at least requires a RISC-V HART to have M/U-mode, and the Sswg/Smwgd extension at least requires a RISC-V HART to have M/S/U-mode. Signed-off-by: Jim Shu --- target

[PATCH 17/17] hw/riscv: virt: Add WorldGuard support

* Add 'wg=on' option to enable RISC-V WorldGuard * Add wgChecker to protect several resources: DRAM, FLASH, UART. Signed-off-by: Jim Shu --- docs/system/riscv/virt.rst | 20 + hw/riscv/Kconfig | 1 + hw/riscv/virt.c

[PATCH 14/17] hw/misc: riscv_wgchecker: Implement wgchecker slot registers

wgChecker slot is similar to PMP region. SW could program each slot to configure the permission of address range. Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 330 + hw/misc/riscv_worldguard.c | 3 + include/hw/misc/riscv_worldguard.h

[PATCH 04/17] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config

Add a device for RISCV WG global config, which contains the number of worlds, reset value, and trusted WID ... etc. This global config is used by both CPU WG extension and wgChecker devices. Signed-off-by: Jim Shu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[PATCH 08/17] target/riscv: Allow global WG config to set WG CPU callbacks

Some WG CPU functions depend on global WG config (like num-of-world), so we let the global WG config device to set callbacks of a RISC-V HART. Signed-off-by: Jim Shu --- target/riscv/cpu.h | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH 02/17] accel/tcg: memory access from CPU will pass access_type to IOMMU

tion so that IOMMU could return the correct section of specified access_type. Signed-off-by: Jim Shu --- accel/tcg/cputlb.c | 17 ++--- include/exec/cputlb.h| 11 +++ include/exec/exec-all.h | 3 ++- system/physm

Re: [PATCH] target/riscv: support atomic instruction fetch (Ziccif)

Hi Richard, Thank you very much for adding atomic support to translator_ld(). It has been a big help. Hi Alistair, I can rebase the Ziccif patch when Richard's patch has been merged. Jim Shu On Fri, Apr 4, 2025 at 12:41 PM Alistair Francis wrote: > > On Fri, Jun 7, 2024 at 8:15

[PATCH v2 0/4] Several sstc extension fixes

, which should update the timer and IRQ pending bits. Jim Shu (4): target/riscv: Add the checking into stimecmp write function. hw/intc: riscv_aclint: Fix mtime write for sstc extension target/riscv: Fix VSTIP bit in sstc extension. target/riscv: Enable/Disable S/VS-mode Timer when STCE bit

[PATCH v2 3/4] target/riscv: Fix VSTIP bit in sstc extension.

VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will revert it's defined behavior as if sstc extension is not implemented. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/csr.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --

Re: [PATCH v2 0/4] Several sstc extension fixes

Sorry, I forgot to write v2 changes in cover-letter. Changes in v2: - Remove duplicated code in riscv_timer_stce_changed() function - Add sstc spec description in the commit log On Wed, Apr 9, 2025 at 10:51 AM Jim Shu wrote: > > This patch series contains several sstc fixes: > > (1

[PATCH v2 1/4] target/riscv: Add the checking into stimecmp write function.

Preparation commit to let aclint timer to use stimecmp write function. Aclint timer doesn't call sstc() predicate so we need to check inside the stimecmp write function. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/time_helper.c | 19 +-- 1 file ch

[PATCH v2 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

c ch19.2.1. Virtual Supervisor Timer (vstimecmp) Register A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the hip register, whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp Signed-off-by: Jim Shu --- hw/in

[PATCH v2 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu --- target/riscv/csr.c | 44 target/riscv/time_helper.c | 46

Re: [PATCH 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

VSTIP bit in the hip register, whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp I will add the explaination in the commit log in the v2 patchset, thanks. Jim Shu On Fri, Apr 4, 2025 at 11:12 AM Alistair Francis wrote: > > On Thu, Ma

Re: [PATCH 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

OK, I will fix it in the v2 patchset. Jim Shu On Fri, Apr 4, 2025 at 2:03 PM Alistair Francis wrote: > > On Thu, Mar 20, 2025 at 5:24 AM Jim Shu wrote: > > > > Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we > > also need to update S/VS-mode T

[PATCH 0/4] Several sstc extension fixes

, which should update the timer and IRQ pending bits. Jim Shu (4): target/riscv: Add the checking into stimecmp write function. hw/intc: riscv_aclint: Fix mtime write for sstc extension target/riscv: Fix VSTIP bit in sstc extension. target/riscv: Enable/Disable S/VS-mode Timer when STCE bit

Re: [PATCH 0/4] Several sstc extension fixes

Hi, Gentle ping on this patch. Thanks, Jim Shu On Thu, Mar 20, 2025 at 3:22 AM Jim Shu wrote: > > This patch series contains several sstc fixes: > > (1) Writing to ACLINT mtime should also update the period of S/VS-mode > timer, just like M-mode timer. > (2) VSTIP bit

[PATCH 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu --- target/riscv/csr.c | 44 target/riscv/time_helper.c | 51

[PATCH 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

When changing the mtime value, the period of [s|vs]timecmp timers should also be updated like the period of mtimecmp timer. Signed-off-by: Jim Shu --- hw/intc/riscv_aclint.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index db374a7c2d

[PATCH 3/4] target/riscv: Fix VSTIP bit in sstc extension.

VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will revert it's defined behavior as if sstc extension is not implemented. Signed-off-by: Jim Shu --- target/riscv/csr.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/t

[PATCH 1/4] target/riscv: Add the checking into stimecmp write function.

Preparation commit to let aclint timer to use stimecmp write function. Aclint timer doesn't call sstc() predicate so we need to check inside the stimecmp write function. Signed-off-by: Jim Shu --- target/riscv/time_helper.c | 19 +-- 1 file changed, 17 insertions(+), 2 dele

Re: [PATCH v4 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

This is the correct fix, thanks! On Tue, Dec 17, 2024 at 11:39 AM Alistair Francis wrote: > > On Thu, Nov 21, 2024 at 1:41 AM Jim Shu wrote: > > > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > > system doesn't have 32-bit addressable i

Re: [PATCH v4 0/3] Support 64-bit address of initrd

I'm sorry for the wrong ping. The email to apply my patch is placed in the spam mail On Tue, Dec 17, 2024 at 12:01 PM Jim Shu wrote: > > Hi, > > Gentle ping on this patch > > Thanks, > Jim Shu > > > > > > On Wed, Nov 20, 2024 at 11:39 PM Jim Shu

Re: [PATCH v4 0/3] Support 64-bit address of initrd

Hi, Gentle ping on this patch Thanks, Jim Shu On Wed, Nov 20, 2024 at 11:39 PM Jim Shu wrote: > > Support to load DTB after 3GB on RV64 system, so that larger initrd > doesn't be overlapped to DTB. DTB loading now will check if overlapping > to kernel/initrd and

[PATCH v4 2/3] hw/riscv: Add a new struct RISCVBootInfo

Add a new struct RISCVBootInfo to sync boot information between multiple boot functions. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 65 ++ hw/riscv/microchip_pfsoc.c | 11 --- hw/riscv/opentitan.c | 4 ++- hw/riscv/sifive_e.c

[PATCH v4 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 25 - include/hw/riscv/boot.h | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-) diff

[PATCH v4 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 14 +- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/

[PATCH v4 0/3] Support 64-bit address of initrd

and struct RISCVBootInfo - Remove the commit to change #address-cell of 'initrd-[start|end]' Jim Shu (3): hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Add the checking if DTB overlaps to kernel or init

Re: [PATCH v3 2/3] hw/riscv: Add a new struct RISCVBootInfo

On Tue, Nov 12, 2024 at 6:05 AM Daniel Henrique Barboza wrote: > > > > On 11/8/24 4:04 AM, Jim Shu wrote: > > Add a new struct RISCVBootInfo to sync boot information between multiple > > boot functions. > > > > Signed-off-by: Jim Shu > > --- >

Re: [PATCH v3 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

On Tue, Nov 12, 2024 at 5:53 AM Daniel Henrique Barboza wrote: > > > > On 11/8/24 4:04 AM, Jim Shu wrote: > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > > system doesn't have 32-bit addressable issue, we just load DTB to the end

[PATCH v3 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 8 ++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifiv

[PATCH v3 2/3] hw/riscv: Add a new struct RISCVBootInfo

Add a new struct RISCVBootInfo to sync boot information between multiple boot functions. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 65 +- hw/riscv/microchip_pfsoc.c | 12 +++--- hw/riscv/opentitan.c | 5 ++- hw/riscv

[PATCH v3 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 25 - include/hw/riscv/boot.h | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-) diff

[PATCH v3 0/3] Support 64-bit address of initrd

tInfo from machine state to local variables. Changes for v2: - Add DTB overlapping checking and struct RISCVBootInfo - Remove the commit to change #address-cell of 'initrd-[start|end]' Jim Shu (3): hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/riscv: A

Re: [PATCH v2 2/3] hw/riscv: Add a new struct RISCVBootInfo

On Fri, Nov 8, 2024 at 5:33 AM Daniel Henrique Barboza wrote: > > > > On 11/7/24 3:31 AM, Jim Shu wrote: > > Add a new struct RISCVBootInfo to sync boot information between multiple > > boot functions. > > > > Signed-off-by: Jim Shu > > --- >

[PATCH v2 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 24 +++- include/hw/riscv/boot.h | 3 +++ 2 files changed, 26 insertions(+), 1 deletion(-) diff

[PATCH v2 2/3] hw/riscv: Add a new struct RISCVBootInfo

Add a new struct RISCVBootInfo to sync boot information between multiple boot functions. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 66 ++ hw/riscv/microchip_pfsoc.c | 11 ++--- hw/riscv/opentitan.c | 4 +- hw/riscv

[PATCH v2 0/3] Support 64-bit address of initrd

cking and struct RISCVBootInfo - Remove the commit to change #address-cell of 'initrd-[start|end]' Jim Shu (3): hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Add the checking if DTB overlaps to kernel or initrd

[PATCH v2 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 8 ++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifiv

Re: [PATCH 2/2] target/riscv/kvm: Update kvm exts to Linux v6.11

Reviewed-by: Jim Shu On Tue, Sep 24, 2024 at 9:24 PM Andrew Jones wrote: > > On Tue, Sep 24, 2024 at 04:30:01PM GMT, zhouq...@iscas.ac.cn wrote: > > From: Quan Zhou > > > > Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs. > > > > Signed-off-by:

Re: [PATCH 2/2] hw/riscv: Support different address-cells for initrd

in.com/linux/v6.11.4/source/drivers/of/fdt.c#L785 [2] https://elixir.bootlin.com/linux/v6.11.4/source/drivers/of/fdt.c#L857 Thanks, Jim Shu On Tue, Oct 22, 2024 at 3:30 AM Daniel Henrique Barboza wrote: > > > > On 10/21/24 1:09 AM, Jim Shu wrote: > > The cells of 'initrd-

Re: [PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

On Mon, Oct 21, 2024 at 9:42 PM Daniel Henrique Barboza wrote: > > > > On 10/21/24 1:09 AM, Jim Shu wrote: > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > > system doesn't have 32-bit addressable issue, we just load DTB to the end

[PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 8 ++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifiv

[PATCH 0/2] Support 64-bit address of initrd

Support to load DTB after 3GB on RV64 system, so that larger initrd doesn't be overlapped to DTB. Update initrd DT to support different "#address-cells". Verify the patch via running 4GB initramfs on the virt machine. Jim Shu (2): hw/riscv: Support to load DTB after 3GB memory o

[PATCH 2/2] hw/riscv: Support different address-cells for initrd

The cells of 'initrd-start/end' should follow the '#address-cell'. QEMU API could support 1 and 2 cells. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ad

Re: [PATCH] vfio/pci: Fix null pointer deference from error API

On Thu, Sep 12, 2024 at 5:56 PM Cédric Le Goater wrote: > > Hello Jim, > > On 9/12/24 08:36, Jim Shu wrote: > > Hi Cédric, > > > > Thank you very much for the quick response! > > > > I have checked the error API again. It seems to be my porting issue o

Re: [PATCH] vfio/pci: Fix null pointer deference from error API

On Thu, Sep 12, 2024 at 2:18 PM Cédric Le Goater wrote: > > Hello Jim, > > On 9/12/24 07:17, Jim Shu wrote: > > pci_dev_realize() use the local error variable, which requires > > `error_setg()` API to allocate the error object at first. > > > > Signed-off-by:

[PATCH] vfio/pci: Fix null pointer deference from error API

pci_dev_realize() use the local error variable, which requires `error_setg()` API to allocate the error object at first. Signed-off-by: Jim Shu --- hw/vfio/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 0a99e55247..d994ad8bb9 100644

Re: [PATCH v2 2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

On Thu, Aug 8, 2024 at 9:34 PM Peter Maydell wrote: > > On Thu, 1 Aug 2024 at 15:08, Jim Shu wrote: > > > > The memory transactions from DMA could have bus-error in some cases. If > > it is failed, DMA device should send error IRQs. > > > > Signed-off-by

[PATCH v2 3/3] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX

ckets when enabling it. Signed-off-by: Jim Shu --- hw/net/xilinx_axienet.c | 71 - 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 05d41bd548..0ecdc30be6 100644 --- a/hw/net/xilinx_axie

[PATCH v2 0/3] Several fixes of AXI-ethernet/DMA

v2: - Remove redundant RCW1_RX checking in enet_write() - Remove qemu_set_irq() in DeviceState::reset() Fix txlen value in the descriptor status field, DMA error handling, and ethernet/DMA reset flow. Jim Shu (3): hw/dma: xilinx_axidma: Correct the txlen value in the descriptor hw/dma

[PATCH v2 1/3] hw/dma: xilinx_axidma: Correct the txlen value in the descriptor

Currently, txlen is always decremented to 0 before filling to the descriptor. Keep the origin txlen value to have the correct value of descriptor status field. It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver. Signed-off-by: Jim Shu --- hw/dma/xilinx_ax

[PATCH v2 2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

The memory transactions from DMA could have bus-error in some cases. If it is failed, DMA device should send error IRQs. Signed-off-by: Jim Shu --- hw/dma/trace-events| 1 + hw/dma/xilinx_axidma.c | 69 ++ 2 files changed, 50 insertions(+), 20

Re: [PATCH 3/4] hw/dma: xilinx_axidma: Reset qemu_irq when DMA/Stream is reset

Hi Peter, Except DeviceState::reset(), stream_reset() is only used in axidma_write() and axidma_write() has qemu_set_irq() at the end of function. I think this commit could be dropped. I will remove it in the v2 patchset. Thanks, Jim Shu On Mon, Jul 29, 2024 at 11:23 PM Peter Maydell wrote

Re: [PATCH 4/4] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX

Shu. On Mon, Jul 29, 2024 at 11:31 PM Peter Maydell wrote: > > On Fri, 26 Jul 2024 at 06:59, Jim Shu wrote: > > > > When AXI ethernet RX is disabled, it shouldn't send packets to AXI DMA, > > which may let AXI DMA to send RX full IRQs. It is aligned with real AXI &g

Re: [PATCH 0/2] Let gen-vdso tool to use internal ELF header

Hi Richard, Thanks for your feedback. I think it is reasonable. I will drop this patchset. Regards, Jim Shu On Fri, Jul 26, 2024 at 1:28 PM Richard Henderson wrote: > > On 7/26/24 14:32, Jim Shu wrote: > > Let gen-vdso tool to use QEMU's internal ELF header. It could avoid

[PATCH 0/4] Several fixes of AXI-ethernet/DMA

Fix txlen value in the descriptor status field, DMA error handling, and ethernet/DMA reset flow. *** BLURB HERE *** Jim Shu (4): hw/dma: xilinx_axidma: Correct the txlen value in the descriptor hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed hw/dma

[PATCH 2/4] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

The memory transactions from DMA could have bus-error in some cases. If it is failed, DMA device should send error IRQs. Signed-off-by: Jim Shu --- hw/dma/trace-events| 1 + hw/dma/xilinx_axidma.c | 69 ++ 2 files changed, 50 insertions(+), 20

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