在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
> Hi all,
>
> This series addressed a couple of missing Bonito functionalities
> I found when I was trying to test NetBSD against QEMU.
>
> Please review.
Another ping :-)
Thanks
Jiaxun
>
> Thanks
> Jiaxun
>
> Signed-off-by:
mips: Add MT halting and waking of VPEs")
> Signed-off-by: Philippe Mathieu-Daudé
Confirmed with uarch behaviour.
Reviewed-by: Jiaxun Yang
Thanks
Jiaxun
> ---
> Supersedes: <20210427103555.112652-1-f4...@amsat.org>
> v2: Check VPEConf0.MVP bit (hansni)
> ---
> target/mi
在2024年5月6日周一 下午4:31，Jiaxun Yang写道：
> Hi all,
>
> This series implemented propper multiple core support for MIPS
> CPS systsm.
Ping :-)
This is a really long outstanding series, I just want to get some
review before respin.
Thanks
Jiaxun
>
> Previously all CPUs are being im
在2025年5月8日周四 下午3:46，Jiaxun Yang写道：
> Hi all,
>
> This series addressed a couple of missing Bonito functionalities
> I found when I was trying to test NetBSD against QEMU.
Hi Philippe,
A gentle ping :-)
Do you have bandwidth on MIPS recently?
I'm planning to respin my CPS S
在2025年5月26日周一 下午7:05，Philippe Mathieu-Daudé写道：
> Intented to help SeaBIOS development; untested there
> (except with QEMU test suite).
>
> Jiaxun, is it helpful to you?
Hi Philippe,
Thanks for the proposal!
The spec says:
```
HBA Reset (HR): When set by SW, this bit causes an internal reset
在2025年5月19日周一 下午2:24，bibo mao写道：
[...]
>> I don't think there is any disadvantage. I don't really buy the "different
>> machine"
>> justification you made. Paravirt solution tends to have its own behaviour
>> and I don't
>> think it's a bad thing to expose it to users.
> irqchip-in-kernel is s
在2025年5月19日周一 上午9:55，Bibo Mao写道：
[...]
>> It's actually different machine as kernel irqchip is never on par with
>> usermode
>> emulation. This approach is taken by i386 (TYPE_KVM_IOAPIC vs TYPE_IOAPIC),
>> Arm (TYPE_KVM_ARM_ITS vs TYPE_ARM_GICV3_ITS), PowerPC (TYPE_KVM_OPENPIC vs
>> TYPE_OPENP
在2025年5月19日周一 上午8:09，Bibo Mao写道：
> On 2025/5/19 下午2:50, Jiaxun Yang wrote:
>>
>>
>> 在2025年5月19日周一 上午3:56，Bibo Mao写道：
>> [...]
>>>>
>>>> Hi Bibo,
>>>>
>>>> I believe hijacking loongarch_extioi.c is not the proper way to
在2025年5月19日周一 上午3:56，Bibo Mao写道：
[...]
>>
>> Hi Bibo,
>>
>> I believe hijacking loongarch_extioi.c is not the proper way to do it.
>> The sensible solution is to create a TYPE_LOONGARCH_EXTIOI_KVM, which
>> inherits TYPE_LOONGARCH_EXTIOI_COMMON, and let machine create
>> TYPE_LOONGARCH_EXTIOI_
在2025年5月9日周五 上午11:07，Bibo Mao写道：
> Add save and store funtction if irqchip-in-kernel property is enabled,
> it is to get/set ExtIOI irqchip state from KVM kernel.
>
> Signed-off-by: Bibo Mao
> ---
> hw/intc/loongarch_extioi.c | 17 +
> hw/intc/loongarch_extioi_kvm.c | 100
在2025年5月9日周五 上午11:12，Bibo Mao写道：
> Option kernel_irqchip=split is not supported on LoongArch virt machine,
> report error and exit if detect split kernel_irqchip option.
>
> Signed-off-by: Bibo Mao
> ---
> target/loongarch/kvm/kvm.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index
49b4be26393a08eda4f99c8e2ef8a0c455c57bc0..918ee39661004d902d2deb25dd5e782855a11854
100644
--- a/hw
ned-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 202 ++-
hw/pci-host/trace-events | 3 -
2 files changed, 75 insertions(+), 130 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index
1c0d502a1e2dfa3c9803ca219cf505
PciBaseCfg.TRANSx.
Emulating this behavior by PCI IOMMU DMA address space with dynamic
remapping on register writes.
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 113 +++
1 file changed, 113 insertions(+)
diff --git a/hw/pci-host/bonito.c b/hw/pci
PCIMAP controls how PCILO and PCIHi regions map into
PCI memory space.
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c | 37 -
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index
Implement interrupt controller on Bonito north bridge, as well
as PCI INTx mapping as per Fuloong 2E's hardware connection.
pci_bonito_set_irq is renamed to bonito_set_irq to reflect that
it also sets other IRQs on chip.
Signed-off-by: Jiaxun Yang
---
hw/pci-host/bonito.c
Hi all,
This series addressed a couple of missing Bonito functionalities
I found when I was trying to test NetBSD against QEMU.
Please review.
Thanks
Jiaxun
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (5):
hw/pci-host/bonito: Implement ICU
hw/pci-host/bonito: Implement PCIMAP
在2025年4月24日周四 上午5:28，WANG Rui写道：
[...]
>>
>> Hardware manual from official public website should be published at
>> first, and SW follows this, rather than informal HW with FPGA version only.
>
> I agree with your point - the ISA specification should come first, and
> software should follow. Tha
在2025年2月27日二月 下午12:21，bibo mao写道：
[...]
int pin.
>>> Thanks for the information, Would you like to emulate LoongArch32
>>> chiplap FPGA board in qemu side or other LoongArch32 boards?
>>
>> My plan is to use current virt machine (with EXTIOI and so on) for
>> Loon
在2025年2月25日二月 下午12:33，bibo mao写道：
> On 2025/2/25 下午8:08, Jiaxun Yang wrote:
>>
>>
>> 在2025年2月25日二月 上午8:50，bibo mao写道：
>>> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>>>> Hi all,
>>>>
>>>> This series is a collection of small f
在2025年2月25日二月 上午8:50，bibo mao写道：
> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>> Hi all,
>>
>> This series is a collection of small fixes I made to TCG for
>> LoongArch32.
>>
>> There are still many thing broken, especially on CSRs. More
>> series
gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.
Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans
however QEMU
is not performing any check against LA32R so far.
Make it available to ALL.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
b/
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still many thing broken, especially on CSRs. More
series following. However this is sufficient to boot 32bit
kernel.
Thanks for revivewing!
Signed-off-by: Jiaxun Yang
---
Changes in v2:
- Addressing
Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 152 +++--
1 file changed, 122 insertions(+), 30 deletions(-)
diff --git a/target/loongarch/cpu.c b/t
gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
All CSRs are meant to be target_ulong wide in our setting.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h| 14 +++---
target/loongarch/tcg/op_helper.c | 4 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/helper.h b/target/loongarch
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/csr_helper.c | 2 +-
1 file changed, 1 insertion
Those results are all targeting TCGv values, which means they should
be in target_ulong type.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h | 8
target/loongarch/tcg/iocsr_helper.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target
As per LoongArch Reference Manual - Volume 1: Basic Architecture,
4.2.2. IOCSR Access Instructions:
The reading value is described as "writes it to the general register rd
after symbolic expansion." which means it should be sign extended.
Signed-off-by: Jiaxun Yang
---
target/loo
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 5 ++---
3 file
在2025年1月21日一月 下午12:07，Jiaxun Yang写道：
> 在2025年1月21日一月 上午10:36，Thomas Huth写道：
>> We are not aware of anybody still using this machine, support for it
>> has been withdrawn from the Linux kernel (i.e. there also won't be
>> any future development anymore), and we are
在2025年1月21日一月 上午10:36，Thomas Huth写道：
> We are not aware of anybody still using this machine, support for it
> has been withdrawn from the Linux kernel (i.e. there also won't be
> any future development anymore), and we are not aware of any binaries
> online that could be used for regression test
ess first CPU propagate from machine_init()
>
> Based-on: <20250112215835.29320-1-phi...@linaro.org>
> "hw/mips/loongson3: Remove uses of &first_cpu global"
Reviewed-by: Jiaxun Yang
Also tested bootloader stuff :-)
>
> Philippe Mathieu-Daudé (19):
> hw/m
pl -q --terse --no-summary --mailback -
---
Signed-off-by: Jiaxun Yang
---
Changes in v2:
- Add lore masks (philmd) from:
https://lore.kernel.org/qemu-devel/20241224135054.10243-1-phi...@linaro.org/
- Link to v1:
https://lore.kernel.org/r/20241222-b4-config-v1-1-b3667beb3...@flygoa
Signed-off-by: Jiaxun Yang
---
Changes in v3:
- Added PATCH 1 (Richard)
- Link to v2:
https://lore.kernel.org/r/20241224-la-direct-kernel-boot-v2-1-3e8336c54...@flygoat.com
Changes in v2:
- Use extract API for getting bit fields (philmd)
- Mimic arm's load_aarch64_image to handle vmlinu
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c
Convert to use sszie_t to represent size internally to avoid
large image overflowing the size.
Suggested-by: Richard Henderson
Signed-off-by: Jiaxun Yang
---
hw/arm/boot.c | 2 +-
hw/core/loader.c| 4 ++--
include/hw/loader.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions
在2024年12月29日十二月 下午10:30，BALATON Zoltan写道：
> On Sun, 29 Dec 2024, Alex Bennée wrote:
>> BALATON Zoltan writes:
>>
>>> On Sun, 29 Dec 2024, Jiaxun Yang wrote:
>>>> EXCP_SEMIHOSTING can be generated by m68k class CPU with
>>>> HALT instruc
在2024年12月29日十二月 下午3:15，BALATON Zoltan写道：
[...]
>
> Also why use switch for a single case? Why not write
>
> if (!is_hw && cs->exception_index == EXCP_SEMIHOSTING)
Mostly for clarity and matching the style above, see:
if (!is_hw) {
switch (cs->exception_index) {
case EXCP_RT
arget/m68k: Perform the semihosting test during
translate")
Cc: qemu-sta...@nongnu.org
Signed-off-by: Jiaxun Yang
---
Changes in v2:
- hoist both calls to do_interrupt_all (Richard)
- Link to v1:
https://lore.kernel.org/r/20241229-m68k-semihosting-v1-1-db131e2b5...@flygoat.com
---
target/m
a...@nongnu.org
Signed-off-by: Jiaxun Yang
---
target/m68k/op_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index
15bad5dd46518c6e86b6273d4a2b26b3b6f991de..95b3d5cf052c6ffd515afdffd5465550ae3af455
100644
--- a/target/m68k/op
在2024年12月27日十二月 上午5:20，Richard Henderson写道：
[...]
>>> +++ b/configs/targets/loongarch32-softmmu.mak
>>> @@ -0,0 +1,7 @@
>>> +TARGET_ARCH=loongarch32
>>> +TARGET_BASE_ARCH=loongarch
>>> +TARGET_KVM_HAVE_GUEST_DEBUG=y
>>> +TARGET_SUPPORTS_MTTCG=y
>>> +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml
在2024年12月26日十二月 下午10:56，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> la464 CPU is not available on LoongArch32. Use max32 which makes
>> more sense here.
>>
>> Signed-off-by: Jiaxun Yang
>> ---
>> hw/loongarch/virt.c | 4
在2024年12月26日十二月 下午10:55，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Introduce max32 CPU type as it's necessary to demonstrate all
>> features we have in LA32.
>>
>> Signed-off-by: Jiaxun Yang
>>
在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Store internal registers including GPRs, CSRs, and LBT scratchs
>> as target_ulong, as per architecture specification.
>>
>> The only exception here is tlb_misc, as it's
在2024年12月26日十二月 下午9:55，Richard Henderson写道：
[...]
> While this allows the code to compile, (1) the functions are unused and
> (2) they do not
> compute the required results. For me, the latter is concerning.
>
> I'd suggest moving GEN_FALSE_TRANS out of trans_privileged.c.inc, then
>
> #ifdef
在2024年12月26日十二月 下午9:31，Richard Henderson写道：
[...]
>>
>> -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
>> +target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong
>> sz)
>> {
>> uint8_t buf[8];
>> target_ulong mask = ((sz * 8) == 64
All CSRs are meant to be target_ulong wide in our setting.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h| 14 +++---
target/loongarch/tcg/op_helper.c | 4 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/helper.h b/target/loongarch
Use TCGv_i64 for intermediate values and perform truncation as necessary.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
b/target
As per LoongArch Reference Manual - Volume 1: Basic Architecture,
4.2.2. IOCSR Access Instructions:
The reading value is described as "writes it to the general register rd
after symbolic expansion." which means it should be sign extended.
Signed-off-by: Jiaxun Yang
---
target/loo
All TARGET_LOONGARCH64 qapis are also available for LoongArch32 as we
are reusing the same CPU backend implemenation.
Use TARGET_LOONGARCH to identify LoongArch.
Signed-off-by: Jiaxun Yang
---
qapi/machine-target.json | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a
gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/csr_helper.c | 2 +-
1 file changed, 1 insertion
Signed-off-by: Jiaxun Yang
---
MAINTAINERS | 4 ++--
configs/devices/loongarch32-softmmu/default.mak | 7 +++
configs/targets/loongarch32-softmmu.mak | 7 +++
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b
They are not available on 32 bit builds.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 68 --
1 file changed, 38 insertions(+), 30 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
la464 CPU is not available on LoongArch32. Use max32 which makes
more sense here.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index
3a905cf71d46e3c5a29672f7bb73faedf1d29444
Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/
ulong is uint64_t on
existing loongarch64 builds anyway.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 34 ++--
target/loongarch/cpu.h | 132 ++---
target/loongarch/machine.c | 120 -
3
Avoid compiler warning on 32bit. This code path won't be taken anyway.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
All float computations are kept to be 64 bit, fix types for various TCGv.
Performing TCGv type conversion as necessary when interaction with GPR
happens.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_farith.c.inc | 53 +++---
target/loongarch/tcg/insn_trans
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 5 ++---
3 file
Add LoongArch32 Kconfig entry and enable the virt machine for
LoongArch32.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/Kconfig | 2 +-
target/loongarch/Kconfig | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index
Use tl variant whenever possible.
Silent compiler warnings by performing casting for come consts.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_bit.c.inc | 34 ++---
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/loongarch/tcg
eries don't have dependency on each other, and I don't
want to take a pile of patches time by time.
There is a checkpatch error in trans_vec.c.inc inherited from
existing code style.
Thanks for revivewing!
Signed-off-by: Jiaxun Yang
---
Changes in v2:
- Dump all patches made ready so fa
however QEMU
is not performing any check against LA32R so far.
Make it available to ALL.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
b/
LoongArch32 have 32 bit vaddr and 36 bit paddr as per architecture
specification.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu-param.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index
is_la64 should be wired to false on LA32 build.
VA32 CSR check shouldn't be performed in LA32 mode.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.h | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.
Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans
mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32
to adopt different TARGET_LONG size.
min value of divisor is generated from TARGET_LONG_BITS to adopt different
long size as well.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_arith.c.inc | 25
Fix types for various TCGv.
Performing TCGv type conversion as necessary when interaction with GPR
happens.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 70 +
1 file changed, 36 insertions(+), 34 deletions(-)
diff --git a/target
Those results are all targeting TCGv values, which means they should
be in target_ulong type.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h | 8
target/loongarch/tcg/iocsr_helper.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target
在2024年12月24日十二月 下午4:00，Philippe Mathieu-Daudé写道：
[...]
> I'd prefer we avoid macros and use the ld/stN API, passing the
> size as argument:
>
> stn_le_p(&boot_memmap->desc_size, size,
> sizeof(efi_memory_desc_t));
>
> Ideally splitting the patch in 3, first convert to us
Support booting such image by parsing header as per Linux's
specification [1].
This enabled booting vmlinux.efi/vmlinuz.efi shipped by
distros without supplying BIOS.
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
---
Changes in v2:
- Use extract AP
Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR
instructions to prevent illegal instructions.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
Use stl_p to store instructions so that host endian conversion
will be performed.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 99 +++--
1 file changed, 51 insertions(+), 48 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch
old implementation such
as null pointer on empty string, memory desc map_size not set,
incorrect memory map definition and so on.
Reviewed-by: Song Gao
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 220 ++--
include/hw/loongarch/boot.h
Hi all,
This series refactored booting protocol generation code
to better accommodate different host ABI / Alignment and
endianess.
It also enhanced LoongArch32 support.
Thanks
---
v2: Fix building on 32 bit host
Signed-off-by: Jiaxun Yang
---
Changes in v3:
- v3: Split PATCH 2 to ease
在2024年12月24日十二月 下午1:50，Philippe Mathieu-Daudé写道：
> Signed-off-by: Philippe Mathieu-Daudé
> ---
Reviewed-by: Jiaxun Yang
Thanks!
> Based-on: <20241222-b4-config-v1-1-b3667beb3...@flygoat.com>
> ---
> .b4-config | 3 +++
> 1 file changed, 3 insertions(+)
>
>
在2024年12月24日十二月 上午4:25，Konstantin Ryabitsev写道：
> On Sun, Dec 22, 2024 at 04:53:41PM +0000, Jiaxun Yang wrote:
>> +[b4]
>> +send-series-to = qemu-devel@nongnu.org
>> +send-auto-to-cmd = echo
>
> Hmm... does it not work without the above line? If so, can you pl
在2024年12月24日十二月 上午4:03，bibo mao写道：
> On 2024/12/23 上午8:30, Jiaxun Yang wrote:
>> Many distros are shipping raw kernel images (i.e. vmlinux.efi).
>>
>> Support booting such image by parsing header as per Linux's
>> specification [1].
>>
>>
在2024年12月24日十二月 上午1:25，bibo mao写道：
> On 2024/12/24 上午9:15, Jiaxun Yang wrote:
>>
>>
>> 在2024年12月24日十二月 上午12:56，bibo mao写道：
>>> Sorry, I do not know the background.
>>> Now kernel image with EFI format can boot if uefi bios is provided.
>>>
>
在2024年12月23日十二月 下午12:46，Philippe Mathieu-Daudé写道：
> On 23/12/24 00:40, Jiaxun Yang wrote:
>> As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
>> "2.2 Table 2. Application-level basic integer instructions in LA32",
>> rotr.w an
在2024年12月23日十二月 下午12:52，Philippe Mathieu-Daudé写道：
> On 23/12/24 00:40, Jiaxun Yang wrote:
>> As per manual, the source of PGD CSR is relevant to highest bit of
>> BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
>> bit 31 of BADV to determine PGDH
在2024年12月23日十二月 下午11:18，Philippe Mathieu-Daudé写道：
> On 23/12/24 22:01, Jiaxun Yang wrote:
>>
>>
>> 在2024年12月23日十二月 下午3:15，Richard Henderson写道：
>>> On 12/22/24 15:40, Jiaxun Yang wrote:
>>>> @@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_
ble for booting vmlinux.efi without BIOS, as well as raw
kernel built without EFI STUB.
Thanks
>
> Regards
> Bibo Mao
>
> On 2024/12/23 上午8:30, Jiaxun Yang wrote:
>> Many distros are shipping raw kernel images (i.e. vmlinux.efi).
>>
>> Support booting such image by p
在2024年12月23日十二月 下午12:24，Philippe Mathieu-Daudé写道：
> On 23/12/24 13:18, Philippe Mathieu-Daudé wrote:
>> Hi Jiaxun,
>>
>> On 22/12/24 17:53, Jiaxun Yang wrote:
>>> b4 [1] is a convenient tool to manage patch series with mailing list
>>> working flow.
>&
在2024年12月23日十二月 下午3:15，Richard Henderson写道：
> On 12/22/24 15:40, Jiaxun Yang wrote:
>> @@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
>> TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
>> TCGv t0 = make_address_i(ctx, src1, a->im
Many distros are shipping raw kernel images (i.e. vmlinux.efi).
Support booting such image by parsing header as per Linux's
specification [1].
[1]: https://docs.kernel.org/arch/loongarch/booting.html
Signed-off-by: Jiaxun Yang
---
It is based on my previous booting protocol patch
--
As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
"2.2 Table 2. Application-level basic integer instructions in LA32",
rotr.w and rotri.w is a part of LA32 basic integer instructions.
Make it available to ALL.
Signed-off-by: Jiaxun Yang
---
Hi all,
This series is a collection of small fixes I made to TCG for
LoongArch32.
There are still many thing broken, especially on CSRs. More
series following.
Thanks for revivewing, merry christmas!
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (3):
target/loongarch: Enable rotr.w/rotri.w
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/csr_helper.c | 2 +-
1 file changed, 1 insertion
gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.
gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc
Wire up ARM_COMPATIBLE_SEMIHOSTING for LoongArch.
The semihosting ABI (i.e. "dbcl 0xab" for semihosting call and Arm
compatible settings) is confirmed by LA132 (1C103)'s OpenOCD
implementation.
Signed-off-by: Jiaxun Yang
---
configs/targets/loongarch64-linux-user.mak |
pl -q --terse --no-summary --mailback -
---
Signed-off-by: Jiaxun Yang
---
● cc5a4c890fed: Add a b4 configuration file
● checkpatch.pl: 27: WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?
---
Success: 0, Warning: 1, Error: 0
```
```
$ b4 prep -c
Will collect To: addr
Use stl_p to write instructions so that host endian conversion
will be performed.
Replace mailbox read/write on LoongArch32 systems with 32bit IOCSR
instructions to prevent illegal instructions.
Reviewed-by: Song Gao
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 107
Hi all,
This series refactored booting protocol generation code
to better accommodate different host ABI / Alignment and
endianess.
It also enhanced LoongArch32 support.
Thanks
---
v2: Fix building on 32 bit host
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/loongarch/boot
old implementation such
as null pointer on empty string, memory desc map_size not set,
incorrect memory map definition and so on.
Reviewed-by: Song Gao
Signed-off-by: Jiaxun Yang
---
hw/loongarch/boot.c | 220 ++--
include/hw/loongarch/boot.h
在2024年9月30日九月 上午10:10，Philippe Mathieu-Daudé写道：
> Get vCPU endianness from CP0::BE bit.
> Propagate endianness at the board level, using QOM property.
> Remove target-specific endianness knowledge from target/.
For the series:
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Will
在2024年9月23日九月 下午1:34，gaosong写道：
> 在 2024/9/14 下午8:10, Jiaxun Yang 写道:
>> Hi all,
>>
>> This series refactored booting protocol generation code
>> to better accommodate different host ABI / Alignment and
>> endianess.
>>
>> It also enhanced LoongArch3
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