Re: [PATCH 0/6] target/i386: Support new Intel platform Instructions in CPUID enumeration

Kindly ping for any comments. BR, Jiaxi On 12/8/2022 3:19 PM, Jiaxi Chen wrote: > Latest Intel platform Granite Rapids/Sierra Forest has introduced below > new instructions and CPUIDs: > > - CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7] > - AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21

[PATCH 0/6] target/i386: Support new Intel platform Instructions in CPUID enumeration

definitions of the corresponding features in QEMU. [1] Intel ISE: https://cdrdv2.intel.com/v1/dl/getContent/671368 [2] kvm/next: https://git.kernel.org/pub/scm/virt/kvm/kvm.git Jiaxi Chen (6): target/i386: Add support for CMPCCXADD in CPUID enumeration target/i386: Add support for AMX-FP16 in

[PATCH 2/6] target/i386: Add support for AMX-FP16 in CPUID enumeration

or added SW overhead. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 21] Add CPUID definition for AMX-FP16. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH 1/6] target/i386: Add support for CMPCCXADD in CPUID enumeration

CPUID definition for CMPCCXADD. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22b681ca37..a61f936eef 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH 4/6] target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration

dword element size operand. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 4] AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word FEAT_7_1_EDX for this leaf. Add CPUID definition for AVX-VNNI-INT8. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 22

[PATCH 6/6] target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration

Latest Intel platform Granite Rapids has introduced a new instruction - PREFETCHIT0/1, which moves code to memory (cache) closer to the processor depending on specific hints. The bit definition: CPUID.(EAX=7,ECX=1):EDX[bit 14] Add CPUID definition for PREFETCHIT0/1. Signed-off-by: Jiaxi Chen

[PATCH 3/6] target/i386: Add support for AVX-IFMA in CPUID enumeration

: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cd787b3d97..5ba0fc61d2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -875,7 +875,7 @@ FeatureWordInfo

[PATCH 5/6] target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration

definition: CPUID.(EAX=7,ECX=1):EDX[bit 5] Add CPUID definition for AVX-NE-CONVERT. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ea1daf6b7e..4aca5360cc 100644