From: Christian Svensson
This patch adds support for atomic locks and is an adaption from
https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
Tested via the atomic lock implementation of musl
Signed-off-by: Christian Svensson
Signed-off-by: Sebastian Macke
Reviwed-by: Jia Liu
Signed
: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 116
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index b90181d..77b1c35 100644
--- a/target-openrisc
Hi Anthony,
This is my OpenRISC patch queue for 2.3, it have been well tested, please pull.
Thanks to Christian and Sebastian, they made the LD/ST updated.
Regards,
Jia
The following changes since commit 16017c48547960539fcadb1f91d252124f442482:
softfloat: Clarify license status (2015-01-
On Mon, Jan 26, 2015 at 6:18 PM, Sebastian Macke wrote:
> Hi Jia,
>
>
> On 1/26/2015 10:50 AM, Jia Liu wrote:
>>
>> Hi Sebastian, Christian
>>
>> On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke
>> wrote:
>>>
>>> From: Christian Svenss
Hi Sebastian, Christian
On Sun, Jan 25, 2015 at 6:25 PM, Sebastian Macke wrote:
> From: Christian Svensson
>
> This patch adds support for atomic locks
> and is an adaption from
> https://github.com/bluecmd/or1k-qemu/commits/or32-optimize
>
> Tested via the atomic lock implementation of musl
>
, rb, rd, tmp);
> +break;
>
> case 0x36:/* l.sb */
> LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
> -mop = MO_UB;
> -goto do_store;
> +gen_loadstore(dc, op0, ra, rb, rd, tmp);
> +break;
>
> case 0x37:/* l.sh */
> LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
> -mop = MO_TEUW;
> -goto do_store;
> -
> -do_store:
> -{
> -TCGv t0 = tcg_temp_new();
> -tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
> -tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
> -tcg_temp_free(t0);
> -}
> +gen_loadstore(dc, op0, ra, rb, rd, tmp);
> break;
>
> default:
Thank you, it is good to separate the related instructions.
Reviwed-by: Jia Liu
> --
> 2.2.2
>
Regards,
Jia
gt; uint32_t K16;
> #endif
> -op0 = extract32(insn, 16, 8);
> +op0 = extract32(insn, 16, 10);
Thank you for pointing this.
Acked-by: Jia Liu
> #ifdef OPENRISC_DISAS
> K16 = extract32(insn, 0, 16);
> #endif
> --
> 2.2.1
>
Regards,
Jia
..05b59e8 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -45,14 +45,16 @@ enum {
> OR_UART0,
> OR_IDE,
> OR_OPENETH,
> -OR_FRAMEBUFFER
> +OR_FRAMEBUFFER,
> +OR_KEYBOARD,
> };
>
> static hwaddr mem_map[] = {
> [OR_UART0] = 0x9000,
> [OR_IDE] = 0x9e00,
> [OR_OPENETH] = 0x9200,
> -[OR_FRAMEBUFFER] = 0x9100
> +[OR_FRAMEBUFFER] = 0x9100,
> +[OR_KEYBOARD] = 0x9400,
> };
>
>
> @@ -188,7 +190,8 @@ static void openrisc_sim_init(MachineState *machine)
> /* OpenCores FrameBuffer device */
> sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
>
> -
> +/* OpenCores keyboard */
> +sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
>
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
> --
> 1.9.1
>
>
Acked-by: Jia Liu
Regards,
Jia
= DEVICE_CLASS(klass);
> +SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> +k->init = lpc32xx_initfn;
> +dc->vmsd = &vmstate_lpc32xx;
> +}
> +
> +static const TypeInfo lpc32xx_info = {
> + .name = TYPE_LPC32XX,
> +.parent= TYPE_SYS_BUS_DEVICE,
> +.instance_size = sizeof(LPC32XXState),
> +.instance_init = lpc32xx_init,
> +.class_init= lpc32xx_class_init,
> +};
> +
> +static void lpc32xx_register_types(void)
> +{
> +type_register_static(&lpc32xx_info);
> +}
> +
> +type_init(lpc32xx_register_types)
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> index 05b59e8..2199a63 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -47,6 +47,7 @@ enum {
> OR_OPENETH,
> OR_FRAMEBUFFER,
> OR_KEYBOARD,
> +OR_TOUCHSCREEN,
> };
>
> static hwaddr mem_map[] = {
> @@ -55,6 +56,7 @@ static hwaddr mem_map[] = {
> [OR_OPENETH] = 0x9200,
> [OR_FRAMEBUFFER] = 0x9100,
> [OR_KEYBOARD] = 0x9400,
> +[OR_TOUCHSCREEN] = 0x9300,
> };
>
>
> @@ -193,6 +195,9 @@ static void openrisc_sim_init(MachineState *machine)
> /* OpenCores keyboard */
> sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
>
> +/* LPC32XX Touch Screen */
> +sysbus_create_simple("lpc32xx", mem_map[OR_TOUCHSCREEN],
> cpu->env.irq[9]);
> +
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
>
> --
> 1.9.1
>
>
Acked-by: Jia Liu
Regards,
Jia
+s->fb = 0;
> +s->cols = 0;
> +s->rows = 0;
> +s->bpp = 0;
> +}
> +
> +static void ocfb_class_init(ObjectClass *klass, void *data)
> +{
> +DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> +k->init = ocfb_initfn;
> +set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
> +dc->vmsd = &vmstate_ocfb;
> +}
> +
> +static const TypeInfo ocfb_info = {
> +.name = TYPE_OCFB,
> +.parent= TYPE_SYS_BUS_DEVICE,
> +.instance_size = sizeof(OCFBState),
> +.instance_init = ocfb_init,
> +.class_init= ocfb_class_init,
> +};
> +
> +static void ocfb_register_types(void)
> +{
> +type_register_static(&ocfb_info);
> +}
> +
> +type_init(ocfb_register_types)
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> index 80aa5ed..7752d22 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -44,13 +44,15 @@
> enum {
> OR_UART0,
> OR_IDE,
> -OR_OPENETH
> +OR_OPENETH,
> +OR_FRAMEBUFFER
> };
>
> static hwaddr mem_map[] = {
> [OR_UART0] = 0x9000,
> [OR_IDE] = 0x9e00,
> [OR_OPENETH] = 0x9200,
> +[OR_FRAMEBUFFER] = 0x9100
> };
>
>
> @@ -183,6 +185,10 @@ static void openrisc_sim_init(MachineState *machine)
> openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
> mem_map[OR_IDE] + 0x100, cpu->env.irq[15]);
>
> +/* OpenCores FrameBuffer device */
> +sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
> +
> +
>
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
> --
> 1.9.1
>
>
Acked-by: Jia Liu
Regards,
Jia
= openrisc_asim.o
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> new file mode 100644
> index 000..80aa5ed
> --- /dev/null
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -0,0 +1,202 @@
> +/*
> + * OpenRISC simulator with more peripherals
> + *
Hi Richard,
Thank you!
Tested-by: Jia Liu
On Sat, Sep 13, 2014 at 9:45 AM, Richard Henderson wrote:
> Cc: Jia Liu
> Signed-off-by: Richard Henderson
> ---
> cpu-exec.c | 18 --
> target-openrisc/cpu.c | 1 +
> target-openris
Hi Valentin,
On Sat, Aug 23, 2014 at 1:06 AM, Valentin Manea
wrote:
> The LPC32XX is a simple MMIO touch screen device with a Linux device
> driver. The device is suitable for small machines which require mouse
> input but have no suitable bus(SPI, I2C).
>
> Add the LPC32XX device to the default
Hi Valentin,
On Sat, Aug 23, 2014 at 1:05 AM, Valentin Manea
wrote:
> Add support for the OpenCores keyboard device to the default OpenRisc
> machine.
>
> The OpenCores keyboard device is a simple open source keyboard device
> created by the OpenCores project(http://opencores.org/). By default it
Hi Valentin,
On Fri, Aug 22, 2014 at 10:01 PM, Valentin Manea
wrote:
> Hi,
>
> I would like to share this series of patches to improve the openrisc
> machine. Mostly my goal is to have the same features as the web based
> machine and be able to boot qemu with exactly the same images.
> Some f
Hi Valentin,
On Fri, Aug 22, 2014 at 9:12 PM, Valentin Manea
wrote:
> The LPC32XX is a simple MMIO touch screen device with a Linux device
> driver. The device is suitable for small machines which require mouse
> input but have no suitable bus(SPI, I2C).
>
> Add the LPC32XX device to the default
Hi Valentin,
On Fri, Aug 22, 2014 at 9:11 PM, Valentin Manea
wrote:
> Add support for the OpenCores keyboard device to the default OpenRisc
> machine.
>
> The OpenCores keyboard device is a simple open source keyboard device
> created by the OpenCores project(http://opencores.org/). By default i
Hi Valentin,
On Fri, Aug 22, 2014 at 9:10 PM, Valentin Manea
wrote:
> Add support for the OpenCores Framebuffer device and enable it by
> default in the OpenRISC machine.
>
> The OpenCores display device is a simple open source framebuffer device
> created http://opencores.org/project,vgafb
>
> S
architecture.
Thank you, James.
I don't have a Linux test environment for I'm a OS X user,
may you please make a test, please?
>
> Handle it in the same way for these architectures, defining
> TARGET_NR__llseek as TARGET_NR_llseek.
>
> Signed-off-by: James Hogan
> Cc: Ri
From: Richard Henderson
Signed-off-by: Richard Henderson
Acked-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 99 +++--
1 file changed, 32 insertions(+), 67 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc
Hi Anthony,
This is my OpenRISC patch queue for 1.8, it have been well tested, please pull.
Thanks to Richard Henderson, he made the LD/ST updated.
Regards,
Jia
The following changes since commit a4550442b947d2c2b346bd2efc8fe3da16425f4d:
petalogix-ml605: Create the CPU with object_new()
Hi Anthony,
Michael said he had applied the typo patch, then I waited it for days
and didn't find it in master,
so I resend the same patch in my pull request queue.
It is my fault, sorry Michael.
And, Anthony, please applied this one, please.
On Sat, Dec 14, 2013 at 4:45 PM, Jia Liu
ping~~
On Sat, Dec 21, 2013 at 9:47 AM, Jia Liu wrote:
> Hi Anthony,
>
> This is my OpenRISC patch queue for 1.8, it have been well tested, please
> pull.
>
> Thanks to Richard Henderson, he made the LD/ST updated.
> Thanks to Stefan Weil, he fixed a typo.
>
>
From: Richard Henderson
Cc: Jia Liu
Signed-off-by: Richard Henderson
Acked-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 99 +++--
1 file changed, 32 insertions(+), 67 deletions(-)
diff --git a/target-openrisc/translate.c b
From: Stefan Weil
Fix typo in comment (transaltion -> translation).
And I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
Hi Anthony,
This is my OpenRISC patch queue for 1.8, it have been well tested, please pull.
Thanks to Richard Henderson, he made the LD/ST updated.
Thanks to Stefan Weil, he fixed a typo.
Regards,
Jia
The following changes since commit f8251db121c3f051b22a7536b97d160c30bcccd4:
Merge remote
Hi Richard,
On Thu, Dec 12, 2013 at 12:42 AM, Richard Henderson wrote:
> Cc: Jia Liu
> Signed-off-by: Richard Henderson
> ---
> target-openrisc/translate.c | 99
> +++--
> 1 file changed, 32 insertions(+), 67 deletions(-)
>
> Un
e. */
> +/* Writeback SR_F translation space to execution space. */
Thank you very much!
Reviewed-by: Jia Liu
> static inline void wb_SR_F(void)
> {
> int label;
> --
> 1.7.10.4
>
Regards,
Jia
From: Sebastian Macke
The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 45
This patch optimizes for this special case.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/translate.c | 50 -
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/translate.c
Hi Anthony,
Hi Blue,
This is my OpenRISC patch queue for 1.7, it have been well tested, please pull.
Thanks to Sebastian Macke, it made move optimization and fix some bugs.
The following changes since commit 394cfa39ba24dd838ace1308ae24961243947fb8:
Merge remote-tracking branch 'quintela/mi
From: Sebastian Macke
The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/sys_helper.c | 16
1
From: Sebastian Macke
Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/mmu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
From: Sebastian Macke
The test cases did not correctly test for the carry flag.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
tests/tcg/openrisc/test_addc.c | 8 +---
tests/tcg/openrisc/test_addic.c | 10 ++
2 files changed, 11 insertions(+), 7
: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
target-openrisc/interrupt.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 16ef4b3..2153e7e 100644
--- a/target-openrisc
: Sebastian Macke
Reviewed-by: Jia Liu
Signed-off-by: Jia Liu
---
hw/openrisc/cputimer.c | 29 +++--
target-openrisc/cpu.h| 1 +
target-openrisc/sys_helper.c | 38 ++
3 files changed, 38 insertions(+), 30 deletions(-)
diff --git
Hi Sebastian,
On Wed, Oct 30, 2013 at 5:22 AM, Sebastian Macke wrote:
> On 29/10/2013 2:15 PM, Max Filippov wrote:
>>
>> On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke
>> wrote:
>>>
>>> Hi,
>>>
>>> This is the second part of the patches to make the openrisc target faster
>>> and more reliable
Hi Sebastian,
On Mon, Oct 28, 2013 at 9:56 AM, Sebastian Macke wrote:
> On 25/10/2013 5:21 PM, Jia Liu wrote:
>>
>> On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke
>> wrote:
>>>
>>> On 22/10/2013 8:47 PM, Jia Liu wrote:
>>>>
>>&
On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke wrote:
> On 22/10/2013 8:47 PM, Jia Liu wrote:
>>
>> Hi Sebastian,
>>
>> On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke
>> wrote:
>>>
>>> This series is the first part to make the OpenRISC t
C target but which does not break the specification and will
> lead to
> a significant speed improvement.
For v2 0/9 - 9/9
Acked-by: Jia Liu
I'll add some comment into the code to explain why we separate flags from sr
and send a pull request if nobody raise a rejection.
>
>
>
Hi Peter,
On Thu, Oct 17, 2013 at 5:15 PM, Peter Maydell wrote:
> On 17 October 2013 04:17, Jia Liu wrote:
>> On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu wrote:
>>> I'm not sure about why qemu-system-or32 is not working on OS X, is it
>>> a AREG0 problem? May yo
Hi all,
On Fri, Oct 11, 2013 at 10:41 AM, Jia Liu wrote:
> Hi all,
>
> I'm not sure about why qemu-system-or32 is not working on OS X, is it
> a AREG0 problem? May you please give me some suggestion, I want to
> test it on OS X, not Ubuntu any longer.
GCC on OS X is OK, i
Hi Anthony,
Hi Peter,
On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell wrote:
> On 3 October 2013 17:41, Jia Liu wrote:
>> Hi Anthony,
>>
>> This is my OpenRISC patch queue. It originally come from Sebastian Macke,
>> split by me, and I used some comment co
Hi all,
I'm not sure about why qemu-system-or32 is not working on OS X, is it
a AREG0 problem? May you please give me some suggestion, I want to
test it on OS X, not Ubuntu any longer.
Thank you.
Regards,
Jia
Hi Peter,
On Thu, Oct 3, 2013 at 5:00 PM, Peter Maydell wrote:
> On 3 October 2013 17:41, Jia Liu wrote:
>> Hi Anthony,
>>
>> This is my OpenRISC patch queue. It originally come from Sebastian Macke,
>> split by me, and I used some comment come from Stefan Kris
From: Sebastian Macke
Where *software* leaves 0x - 0x2000 unmapped, the hardware should
still allow for this area to be mapped.
Signed-off-by: Sebastian Macke
Signed-off-by: Stefan Kristiansson
Reviewed-by: Jia Liu
---
target-openrisc/mmu.c | 7 ---
1 file changed, 7 deletions
Hi Anthony,
This is my OpenRISC patch queue. It originally come from Sebastian Macke,
split by me, and I used some comment come from Stefan Kristiansson.
Please pull.
This patch set correct two problems. The first one corrects one obvious
bug concerning the handling of page faults while reading
From: Sebastian Macke
The result of (rw & 0) is always zero and therefore a logic false.
The whole comparison will therefore never be executed, it is a obvious bug,
we should use !(rw & 1) here.
Signed-off-by: Sebastian Macke
Reviewed-by: Jia Liu
---
target-openrisc/mmu.c | 2 +-
On Wed, Oct 2, 2013 at 2:15 PM, Stefan Kristiansson
wrote:
> On Wed, Oct 2, 2013 at 8:33 AM, Jia Liu wrote:
>>
>> Hi Sebastian,
>>
>> On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke
>> wrote:
>> > Hi,
>> >
>> > this patch corrects
Hi Sebastian,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke wrote:
> Hi,
>
> this patch corrects two problems for the OpenRISC Target in QEMU. The first
> one corrects one obvious bug
> concerning the handling of page faults while reading from a page.
@@ -102,7 +102,7 @@ int cpu_openrisc_get_p
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
> return 0;
> }
> /* XXX */
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index 2e26fd1..d0527e5 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -249,7 +249,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> /* Map a single page. */
> phys_addr &= TARGET_PAGE_MASK;
> address &= TARGET_PAGE_MASK;
> -tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
> +tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
> return 0;
> }
>
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 164b34b..5952ed8 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -74,10 +74,10 @@ void tlb_fill(CPUState *cs,
> vaddr, is_write, mmu_idx, paddr, ret);
>
> if (ret == 0) {
> -tlb_set_page(env,
> -vaddr & TARGET_PAGE_MASK,
> -paddr & TARGET_PAGE_MASK,
> -access, mmu_idx, page_size);
> +tlb_set_page(cs,
> + vaddr & TARGET_PAGE_MASK,
> + paddr & TARGET_PAGE_MASK,
> + access, mmu_idx, page_size);
> } else {
> cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
range if translation is valid */
> if (TTE_IS_VALID(tlb->tte)) {
> +CPUState *cs = CPU(sparc_env_get_cpu(env1));
>
> mask = 0xe000ULL;
> mask <<= 3 * ((tlb->tte >> 61) & 3);
> @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *t
per_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> int asi, int size)
> {
> +SPARCCPU *cpu = sparc_env_get_cpu(env);
> +
> #ifdef DEBUG_ASI
> dump_asi("write", addr, asi, size, val);
> #endif
> @@ -1865,7 +1867,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
> addr, target_ulong val,
> #ifdef DEBUG_MMU
> dump_mmu(stdout, fprintf, env);
> #endif
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> }
> return;
> }
> @@ -1954,13 +1956,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
> addr, target_ulong val,
> env->dmmu.mmu_primary_context = val;
> /* can be optimized to only flush MMU_USER_IDX
> and MMU_KERNEL_IDX entries */
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> break;
> case 2: /* Secondary context */
> env->dmmu.mmu_secondary_context = val;
> /* can be optimized to only flush MMU_USER_SECONDARY_IDX
> and MMU_KERNEL_SECONDARY_IDX entries */
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> break;
> case 5: /* TSB access */
> DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
> @@ -2389,7 +2391,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr
> addr,
> /* flush neverland mappings created during no-fault mode,
> so the sequential MMU faults report proper fault types */
> if (env->mmuregs[0] & MMU_NF) {
> -tlb_flush(env, 1);
> +tlb_flush(cs, 1);
> }
> }
> #else
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index a353dab..3f3de4c 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> int cpu_load(QEMUFile *f, void *opaque, int version_id)
> {
> CPUSPARCState *env = opaque;
> +SPARCCPU *cpu = sparc_env_get_cpu(env);
> int i;
> uint32_t tmp;
>
> @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
> qemu_get_be64s(f, &env->ssr);
> cpu_get_timer(f, env->hstick);
> #endif
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> return 0;
> }
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index dcf3b16..a317217 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -141,7 +141,7 @@ static void uc32_cpu_initfn(Object *obj)
> env->regs[31] = 0x0300;
> #endif
>
> -tlb_flush(env, 1);
> +tlb_flush(cs, 1);
>
> if (tcg_enabled() && !inited) {
> inited = true;
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index f91ed93..8de6a33 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -57,6 +57,8 @@ uint32_t HELPER(clz)(uint32_t x)
> void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
> uint32_t cop)
> {
> +UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> /*
> * movc pp.nn, rn, #imm9
> * rn: UCOP_REG_D
> @@ -125,7 +127,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val,
> uint32_t creg,
> case 6:
> if ((cop <= 6) && (cop >= 2)) {
> /* invalid all tlb */
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> return;
> }
> break;
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 5771841..70937b6 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -479,10 +479,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env,
> uint32_t pc, uint32_t vaddr)
>
> void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
> {
> +XtensaCPU *cpu = xtensa_env_get_cpu(env);
> +
> v = (v & 0xff00) | 0x1;
> if (v != env->sregs[RASID]) {
> env->sregs[RASID] = v;
> -tlb_flush(env, 1);
> +tlb_flush(CPU(cpu), 1);
> }
> }
target-openrisc: Tested-by: Jia Liu
>
> --
> 1.8.1.4
>
TENSA_OPTION_UNALIGNED_EXCEPTION) &&
> !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT))
> {
> - cpu_restore_state(env, retaddr);
> +cpu_restore_state(ENV_GET_CPU(env), retaddr);
> HELPER(exception_cause_vaddr)(env,
> env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
> }
> @@ -79,7 +79,7 @@ void tlb_fill(CPUState *cs,
> paddr & TARGET_PAGE_MASK,
> access, mmu_idx, page_size);
> } else {
> -cpu_restore_state(env, retaddr);
> +cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
> }
> }
> diff --git a/translate-all.c b/translate-all.c
> index ef34936..5673420 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -249,8 +249,9 @@ static int cpu_restore_state_from_tb(TranslationBlock
> *tb, CPUArchState *env,
> return 0;
> }
>
> -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr)
> +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
> {
> +CPUArchState *env = cpu->env_ptr;
> TranslationBlock *tb;
>
> tb = tb_find_pc(retaddr);
> diff --git a/user-exec.c b/user-exec.c
> index e149c97..75c6d54 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
> unsigned long address,
> return 1; /* the MMU fault was handled without causing real CPU
> fault */
> }
> /* now we have a real cpu fault */
> -cpu_restore_state(env, pc);
> +cpu_restore_state(cpu, pc);
>
> /* we restore the process signal mask as the sigreturn should
> do it (XXX: use sigsetjmp) */
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
pu_restore_state(env, retaddr);
> }
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index cd2cbef..3efc6a8 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env,
> uint32_t x, uint32_t i)
> #define SHIFT 3
> #include "exec/softmmu_template.h"
>
> -void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
>int mmu_idx, uintptr_t retaddr)
> {
> -UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int ret;
>
> -ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> +ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> +UniCore32CPU *cpu = UNICORE32_CPU(cs);
> +CPUUniCore32State *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 2e006e4..cc1d5e2 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -59,9 +59,11 @@ static void do_unaligned_access(CPUXtensaState *env,
> }
> }
>
> -void tlb_fill(CPUXtensaState *env,
> -target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
> +void tlb_fill(CPUState *cs,
> + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t
> retaddr)
> {
> +XtensaCPU *cpu = XTENSA_CPU(cs);
> +CPUXtensaState *env = &cpu->env;
> uint32_t paddr;
> uint32_t page_size;
> unsigned access;
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
lper.c b/target-sparc/ldst_helper.c
> index 973fcb6..65ce724 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2443,7 +2443,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write, int mmu_idx,
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> -cpu_loop_exit(env);
> +cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 3efc6a8..c2bf834 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t
> excp)
> CPUState *cs = CPU(uc32_env_get_cpu(env));
>
> cs->exception_index = excp;
> -cpu_loop_exit(env);
> +cpu_loop_exit(cs);
> }
>
> static target_ulong asr_read(CPUUniCore32State *env)
> @@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
> is_write,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> -cpu_loop_exit(env);
> +cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index cc1d5e2..17d7f35 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -104,7 +104,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
> if (excp == EXCP_DEBUG) {
> env->exception_taken = 0;
> }
> -cpu_loop_exit(env);
> +cpu_loop_exit(cs);
> }
>
> void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t
> cause)
> @@ -390,7 +390,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc,
> uint32_t intlevel)
> (intlevel << PS_INTLEVEL_SHIFT);
> check_interrupts(env);
> if (env->pending_irq_level) {
> -cpu_loop_exit(env);
> +cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
> return;
> }
>
> diff --git a/user-exec.c b/user-exec.c
> index dbb9c8d..e149c97 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -40,12 +40,12 @@
>
> static void exception_action(CPUArchState *env1)
> {
> -#if defined(TARGET_I386)
> CPUState *cpu = ENV_GET_CPU(env1);
>
> +#if defined(TARGET_I386)
> raise_exception_err(env1, cpu->exception_index, env1->error_code);
> #else
> -cpu_loop_exit(env1);
> +cpu_loop_exit(cpu);
> #endif
> }
target-openrisc: Tested-by: Jia Liu
>
> --
> 1.8.1.4
>
bp, &cs->breakpoints, entry) {
> if (ctx.pc == bp->pc) {
> /* We have hit a breakpoint - make sure PC is up-to-date
> */
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 9443713..6c1ff68 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s)
>
> scc->parent_reset(s);
>
> -memset(env, 0, offsetof(CPUSPARCState, breakpoints));
> +memset(env, 0, offsetof(CPUSPARCState, version));
> tlb_flush(env, 1);
> env->cwp = 0;
> #ifndef TARGET_SPARC64
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index cfa1e0d..69c6154 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -421,6 +421,7 @@ struct CPUSPARCState {
>
> CPU_COMMON
>
> +/* Fields from here on are preserved across CPU reset. */
> target_ulong version;
> uint32_t nwindows;
>
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 73f8b9c..bc52c85 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -5254,8 +5254,8 @@ static inline void
> gen_intermediate_code_internal(SPARCCPU *cpu,
> max_insns = CF_COUNT_MASK;
> gen_tb_start();
> do {
> -if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> -QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> +if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> +QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> if (dc->pc != pc_start)
> save_state(dc);
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index 1246895..b4bee99 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -1925,8 +1925,8 @@ static inline void
> gen_intermediate_code_internal(UniCore32CPU *cpu,
>
> gen_tb_start();
> do {
> -if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> -QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> +if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> +QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> gen_set_pc_im(dc->pc);
> gen_exception(EXCP_DEBUG);
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index 24343bd..55d4448 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -2871,10 +2871,11 @@ invalid_opcode:
>
> static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
> {
> +CPUState *cs = CPU(xtensa_env_get_cpu(env));
> CPUBreakpoint *bp;
>
> -if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> -QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> +if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> +QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> tcg_gen_movi_i32(cpu_pc, dc->pc);
> gen_exception(dc, EXCP_DEBUG);
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
_name(oc)));
> -env = &cpu->env;
> -env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index c8d8c55..9443713 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -84,7 +84,6 @@ static int cpu_sparc_register(CPUSPARCState *env, const
> char *cpu_model)
> env->def->features |= CPU_FEATURE_FLOAT128;
> }
> #endif
> -env->cpu_model_str = cpu_model;
> env->version = def->iu_version;
> env->fsr = def->fpu_version;
> env->nwindows = def->nwindows;
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index 4e90cf3..eece271 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -37,7 +37,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
> }
> cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
> env = &cpu->env;
> -env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
--git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index ef12a0a..9eb096e 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -842,7 +842,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr
> addr)
> SPARCCPU *cpu = SPARC_CPU(cs);
> CPUSPARCState *env = &cpu->env;
> hwaddr phys_addr;
> -int mmu_idx = cpu_mmu_index(env);
> +int mmu_idx = cpu_mmu_index(cs);
> MemoryRegionSection section;
>
> if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 36615f1..73f8b9c 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -5241,7 +5241,7 @@ static inline void
> gen_intermediate_code_internal(SPARCCPU *cpu,
> last_pc = dc->pc;
> dc->npc = (target_ulong) tb->cs_base;
> dc->cc_op = CC_OP_DYNAMIC;
> -dc->mem_idx = cpu_mmu_index(env);
> +dc->mem_idx = cpu_mmu_index(cs);
> dc->def = env->def;
> dc->fpu_enabled = tb_fpu_enabled(tb->flags);
> dc->address_mask_32bit = tb_am_enabled(tb->flags);
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index 1cfe50a..3ed9ea3 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -23,6 +23,13 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[31] = value;
> }
>
> +static int uc32_cpu_mmu_index(const CPUState *cs)
> +{
> +UniCore32CPU *cpu = UNICORE32_CPU(cs);
> +
> +return (cpu->env.uncached_asr & ASR_M) == ASR_MODE_USER ? MMU_USER_IDX :
> 0;
> +}
> +
> static bool uc32_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request &
> @@ -147,6 +154,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void
> *data)
> cc->has_work = uc32_cpu_has_work;
> cc->do_interrupt = uc32_cpu_do_interrupt;
> cc->dump_state = uc32_cpu_dump_state;
> +cc->mmu_index = uc32_cpu_mmu_index;
> cc->set_pc = uc32_cpu_set_pc;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 1db7419..07693d5 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -137,10 +137,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
> target_ulong address, int
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index(CPUUniCore32State *env)
> -{
> -return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
> -}
>
> #include "exec/cpu-all.h"
> #include "cpu-qom.h"
> diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
> index 46573c6..f99feaa 100644
> --- a/target-xtensa/cpu.c
> +++ b/target-xtensa/cpu.c
> @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int xtensa_cpu_mmu_index(const CPUState *cs)
> +{
> +XtensaCPU *cpu = XTENSA_CPU(cs);
> +
> +return xtensa_get_cring(&cpu->env);
> +}
> +
> static bool xtensa_cpu_has_work(CPUState *cs)
> {
> XtensaCPU *cpu = XTENSA_CPU(cs);
> @@ -142,6 +149,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
> *data)
> cc->has_work = xtensa_cpu_has_work;
> cc->do_interrupt = xtensa_cpu_do_interrupt;
> cc->dump_state = xtensa_cpu_dump_state;
> +cc->mmu_index = xtensa_cpu_mmu_index;
> cc->set_pc = xtensa_cpu_set_pc;
> cc->gdb_read_register = xtensa_cpu_gdb_read_register;
> cc->gdb_write_register = xtensa_cpu_gdb_write_register;
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index de27c8c..4fdaf20 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -472,11 +472,6 @@ static inline xtensa_tlb_entry
> *xtensa_tlb_get_entry(CPUXtensaState *env,
> #define MMU_MODE2_SUFFIX _ring2
> #define MMU_MODE3_SUFFIX _ring3
>
> -static inline int cpu_mmu_index(CPUXtensaState *env)
> -{
> -return xtensa_get_cring(env);
> -}
> -
> #define XTENSA_TBFLAG_RING_MASK 0x3
> #define XTENSA_TBFLAG_EXCM 0x4
> #define XTENSA_TBFLAG_LITBASE 0x8
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
+cc->has_work = sparc_cpu_has_work;
> cc->do_interrupt = sparc_cpu_do_interrupt;
> cc->dump_state = sparc_cpu_dump_state;
> #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 41194ec..adf6557 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -747,15 +747,6 @@ static inline bool tb_am_enabled(int tb_flags)
> #endif
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
> -CPUSPARCState *env1 = &sparc_cpu->env;
> -
> -return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
> - cpu_interrupts_enabled(env1);
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index 3f78208..1cfe50a 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[31] = value;
> }
>
> +static bool uc32_cpu_has_work(CPUState *cs)
> +{
> +return cs->interrupt_request &
> +(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> +}
> +
> static inline void set_feature(CPUUniCore32State *env, int feature)
> {
> env->features |= feature;
> @@ -138,6 +144,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void
> *data)
> dc->realize = uc32_cpu_realizefn;
>
> cc->class_by_name = uc32_cpu_class_by_name;
> +cc->has_work = uc32_cpu_has_work;
> cc->do_interrupt = uc32_cpu_do_interrupt;
> cc->dump_state = uc32_cpu_dump_state;
> cc->set_pc = uc32_cpu_set_pc;
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 967511e..1db7419 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -160,10 +160,4 @@ static inline void
> cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc
> void uc32_translate_init(void);
> void switch_mode(CPUUniCore32State *, int);
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> -return cpu->interrupt_request &
> -(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> -}
> -
> #endif /* QEMU_UNICORE32_CPU_H */
> diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
> index c19d17a..46573c6 100644
> --- a/target-xtensa/cpu.c
> +++ b/target-xtensa/cpu.c
> @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool xtensa_cpu_has_work(CPUState *cs)
> +{
> +XtensaCPU *cpu = XTENSA_CPU(cs);
> +
> +return cpu->env.pending_irq_level;
> +}
> +
> /* CPUClass::reset() */
> static void xtensa_cpu_reset(CPUState *s)
> {
> @@ -132,6 +139,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
> *data)
> cc->reset = xtensa_cpu_reset;
>
> cc->class_by_name = xtensa_cpu_class_by_name;
> +cc->has_work = xtensa_cpu_has_work;
> cc->do_interrupt = xtensa_cpu_do_interrupt;
> cc->dump_state = xtensa_cpu_dump_state;
> cc->set_pc = xtensa_cpu_set_pc;
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index 95103e9..de27c8c 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -519,11 +519,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState
> *env, target_ulong *pc,
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
>
> -static inline int cpu_has_work(CPUState *cpu)
> -{
> -CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
> -
> -return env->pending_irq_level;
> -}
> -
> #endif
target-openrisc: Tested-by: Jia Liu
> --
> 1.8.1.4
>
Hi Peter,
On Fri, Aug 23, 2013 at 10:09 PM, Peter Maydell
wrote:
> On 21 August 2013 03:06, Jia Liu wrote:
>> This is my OpenRISC patch queue for 1.7, it have been well tested, please
>> pull.
>>
>>
>> -----------
is not necessary for masking.
Simply use (cpu->env.picsr & cpu->env.picmr).
Signed-off-by: Xi Wang
Acked-by: Jia Liu
---
hw/openrisc/pic_cpu.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c
index ca0b7c1..3
git or32
for you to fetch changes up to 7717f248eebdcfe6de400404d0cf65dcb3633308:
hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() (2013-08-21
09:31:42 +0800)
--------
Jia Liu (3):
hw/openrisc: Avoid using uninitial
In C99 signed shift (1 << 31) is undefined behavior, since the result
exceeds INT_MAX. Use 1U instead and move the shift after the check.
Signed-off-by: Xi Wang
Acked-by: Jia Liu
---
hw/openrisc/pic_cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/op
!qtest_enabled()) {
^~~
hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
cpu->env.pc = entry;
^
Fix this by not attempting to change the CPU's starting PC unless
we actually loaded a kernel.
Signed-off-by: Peter Maydell
Hi Peter,
On Tue, Aug 20, 2013 at 9:00 PM, Peter Maydell wrote:
> Ping for qemu-trivial now 1.7 is open.
Thank you, I'll send a PULL very soon.
>
> thanks
> -- PMM
>
> On 5 August 2013 19:24, Peter Maydell wrote:
>> clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
>>
Hi Xi,
On Wed, Aug 14, 2013 at 1:55 PM, Xi Wang wrote:
> In C99 signed shift (1 << 31) is undefined behavior, since the result
> exceeds INT_MAX. Use 1U instead and move the shift after the check.
>
> Cc: Jia Liu
> Cc: Paolo Bonzini
> Signed-off-by: Xi Wang
> ---
&
Consider the masking of PICSR and PICMR:
>
> ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i)))
>
> To correctly mask bits, we should use the bitwise AND "&" rather than
> the logical AND "&&". Al
Hi Richard,
On Sat, Aug 10, 2013 at 3:19 AM, Richard Henderson wrote:
> We have one host platform (aarch64), and three target platforms
> (openrisc, unicore32, xtensa) with no built-in disassembly support,
> thanks largely to gplv3 silliness.
Thank you for doing this for or32.
>
> Here's a firs
> }
> -}
>
> -cpu->env.pc = entry;
> + cpu->env.pc = entry;
> +}
> }
>
> static void openrisc_sim_init(QEMUMachineInitArgs *args)
Thank you for using clang test it.
Reviewed-by: Jia Liu
> --
> 1.7.9.5
>
Regards,
Jia
VMSTATE_END_OF_LIST()
> };
> diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
> index 6f864fe..372b261 100644
> --- a/target-openrisc/machine.c
> +++ b/target-openrisc/machine.c
> @@ -45,7 +45,6 @@ const VMStateDescription vmstate_openrisc_cpu = {
> .minimum_version_id = 1,
> .minimum_version_id_old = 1,
> .fields = (VMStateField[]) {
> -VMSTATE_CPU(),
> VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
> VMSTATE_END_OF_LIST()
> }
Tested-by: Jia Liu
> --
> 1.8.1.4
>
Regards,
Jia
> still registered for AlphaCPU (fe31e7374299c0c6172ce618b29bf2fecbd881c7)
> and OpenRISCCPU (da69721460e652072b6a3dd52b7693da21ffe237). Fix this.
>
> Cc: Richard Henderson
> Cc: Jia Liu
> Signed-off-by: Andreas Färber
> ---
> exec.c | 5 -
> 1 file changed, 4 insert
Hi Xi,
On Tue, Jan 22, 2013 at 11:57 PM, Xi Wang wrote:
> A correct mask should be `x & (1 << i)', rather than `x && (1 << i)'.
>
> Also, in C99 signed shift (1 << 31) is undefined behavior, since the
> result exceeds INT_MAX; use 1U instead.
>
> Signed-off-by: Xi Wang
> ---
> hw/openrisc_pic.c
644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -45,10 +45,11 @@ static void moxie_cpu_reset(CPUState *s)
>
> static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
> {
> -MoxieCPU *cpu = MOXIE_CPU(dev);
> +CPUState *cs = CPU(dev);
> Moxie
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu
Reviewed-by: Peter Maydell
Reviewed-by: Andreas Färber
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc
We should free typename here.
Signed-off-by: Jia Liu
Reviewed-by: Andreas Färber
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
Indent typo.
Signed-off-by: Jia Liu
Reviewed-by: Peter Maydell
Reviewed-by: Andreas Färber
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..250f5b5 100644
--- a/hw/openrisc
openrisc_cpu_class_by_name (2013-07-23
18:32:30 +0800)
Jia Liu (3):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename in openrisc_cpu_class_by_name
hw
Indent typo.
Signed-off-by: Jia Liu
Reviewed-by: Peter Maydell
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..250f5b5 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw
We should free typename here.
Signed-off-by: Jia Liu
Reviewed-by: Andreas Färber
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
typename free.
Jia Liu (3):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename in openrisc_cpu_class_by_name
hw/openrisc/openrisc_sim.c | 6 +++---
target-openrisc/cpu.c | 1 +
2 files changed, 4 insertions(+), 3 deletions
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu
Reviewed-by: Peter Maydell
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell wrote:
> On 22 July 2013 10:42, Jia Liu wrote:
>> Hi Andreas and Peter,
>>
>> On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell
>> wrote:
>>> This looks a bit odd. The commit message suggests it's an
>
On Mon, Jul 22, 2013 at 5:43 PM, Peter Maydell wrote:
> On 22 July 2013 10:42, Jia Liu wrote:
>> Hi Andreas and Peter,
>>
>> On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell
>> wrote:
>>> This looks a bit odd. The commit message suggests it's an
>
On Mon, Jul 22, 2013 at 5:41 PM, Peter Maydell wrote:
> On 22 July 2013 10:37, Jia Liu wrote:
>> Hi Andreas,
>>
>> On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu wrote:
>>> We should free typename here.
>>>
>>> Signed-off-by: Jia Liu
>>
>>
Hi Andreas and Peter,
On Mon, Jul 22, 2013 at 5:29 PM, Peter Maydell wrote:
> On 22 July 2013 09:56, Jia Liu wrote:
>> Fix cpu_model by name, make any and or1200 works both OK.
>>
>> Signed-off-by: Jia Liu
>> ---
>> target-openrisc/cpu.c | 16
Hi Andreas,
On Mon, Jul 22, 2013 at 4:56 PM, Jia Liu wrote:
> We should free typename here.
>
> Signed-off-by: Jia Liu
Sorry I didn't know I need add Signed-off-by: Andreas Färber here.
> ---
> target-openrisc/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e348df0..6637166 100644
--- a/target-openrisc
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 250f5b5..a08f27c
Indent typo.
Signed-off-by: Jia Liu
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 924438b..250f5b5 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -96,7
We should free typename here.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static
, make any and or1200 works both OK.
Jia Liu (4):
hw/openrisc: Indent typo
hw/openrisc: Use stderr output instead of qemu_log
target-openrisc: Free typename
target-openrisc: Fix cpu_model by name
hw/openrisc/openrisc_sim.c | 6 +++---
target-openrisc/cpu.c | 17 +
2 files
Hi Peter,
On Fri, Jul 19, 2013 at 5:27 PM, Peter Maydell wrote:
> On 19 July 2013 01:25, Jia Liu wrote:
>> Hi Peter,
>>
>> On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell
>> wrote:
>>> Ping?
>>>
>>
>> Thank you, it looks good to me, ple
Hi Peter,
On Thu, Jul 18, 2013 at 6:18 PM, Peter Maydell wrote:
> Ping?
>
Thank you, it looks good to me, please push it.
> thanks
> -- PMM
>
> On 6 July 2013 21:44, Peter Maydell wrote:
>> OpenRISC uses the asm-generic versions of target_stat and
>> target_stat64, but it was incorrectly using
Hi Andreas,
On Tue, Jul 16, 2013 at 10:19 PM, Andreas Färber wrote:
> Am 16.07.2013 04:00, schrieb Jia Liu:
>> We should free typename here.
>>
>> Signed-off-by: Jia Liu
>> ---
>> target-openrisc/cpu.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
&
On Tue, Jul 16, 2013 at 10:00 AM, Jia Liu wrote:
> Fix cpu_model by name, make any and or1200 works both OK.
>
Sorry, I forgot add V2 in title.
> Signed-off-by: Jia Liu
> ---
> target-openrisc/cpu.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-
On Tue, Jul 16, 2013 at 10:00 AM, Jia Liu wrote:
> We should free typename here.
>
Sorry, I forgot add V2 in title.
> Signed-off-by: Jia Liu
> ---
> target-openrisc/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target-openrisc/cpu.c b/target-openri
We should use stderr output instead of qemu_log in order to output ErrMsg
onto the screen.
Signed-off-by: Jia Liu
---
hw/openrisc/openrisc_sim.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index f0dabb9
Fix cpu_model by name, make any and or1200 works both OK.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index e348df0..6637166 100644
--- a/target-openrisc
We should free typename here.
Signed-off-by: Jia Liu
---
target-openrisc/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 6d40f1b..e348df0 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -99,6 +99,7 @@ static
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