Re: [PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts

I intended to separate the S-mode and M-mode handling. Do you think this change could improve performance? Thanks, Jay Chang On Tue, Jul 1, 2025 at 11:46 AM Nutty Liu wrote: > On 7/1/2025 11:00 AM, Jay Chang wrote: > > RISC-V AIA Spec states: > > "For a machine-level en

[PATCH v3 0/2] Add S-mode checks for delegation-related CSRs

updated predicate in aia_smode32. Change log: V3: * Add cover letter Jay Chang (2): target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts target/riscv: Restrict midelegh access to S-mode harts target/riscv/csr.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.48.1

[PATCH v3 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --gi

[PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang --- ta

Re: [PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

Hi, Gentle ping on this patch. Thanks, Jay Chang On Tue, Apr 1, 2025 at 6:34 PM Jay Chang wrote: > RISC-V Privileged Spec states: > "In harts with S-mode, the medeleg and mideleg registers must exist, and > setting a bit in medeleg or mideleg will delegate the corresponding

[PATCH v5 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 48

[PATCH v5 0/2] Extend and configure PMP region count

uld set its own default if they want. (based on feedback from Daniel) Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/riscv/cpu.c| 48 ++- target/riscv/cpu.h| 3 +- target/ri

[PATCH v5 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

Re: [PATCH v4 2/2] target/riscv: Make PMP region count configurable

*Hi Daniel,* You're absolutely right — thanks for pointing it out and providing the fix! Would you like me to send out a v5 patch incorporating your changes? Best Regards Jay Chang On Thu, Jun 5, 2025 at 2:20 AM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: >

[PATCH v3 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. Change log: V3: * Changed `pmp_regions` type from `uint16_t` to `uint8_t` * Introduced `OLD_MAX_RISCV_PMPS` macro

[PATCH v4 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 54

[PATCH v4 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

[PATCH v4 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. Change log: V4: * Changed `pmp_regions` type from `uint16_t` to `uint8_t` * Introduced `OLD_MAX_RISCV_PMPS` macro

[PATCH v3 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 54

[PATCH v3 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

[PATCH v2 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu_bits.h | 60 +++ target/riscv/csr.c |

[PATCH v2 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. change log: V2: * Rebase on riscv-to-apply.next Jay Chang (2): target/riscv: Extend PMP region up to 64 target/ri

[PATCH v2 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu.c| 54

Re: [PATCH 2/2] target/riscv: Make PMP region count configurable

I will send v2 patch Jay Chang On Thu, Apr 24, 2025 at 6:55 PM Alistair Francis wrote: > On Mon, Apr 21, 2025 at 7:48 PM Jay Chang wrote: > > > > Previously, the number of PMP regions was hardcoded to 16 in QEMU. > > This patch replaces the fixed value with a ne

[PATCH 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu_bits.h | 60 +++ target/riscv/csr.c |

[PATCH 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu.c | 46

[PATCH 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/ri

[PATCH 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 7 +-- 1 fi

[PATCH v2 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 7 +-- 1 fi

[PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/ta

Re: [PATCH 2/2] target/riscv: Restrict midelegh access to S-mode harts

enrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 3/18/25 4:01 AM, Jay Chang wrote: > > RISC-V AIA Spec states: > > "For a machine-level environment, extension Smaia encompasses all added > > CSRs and all modifications to interrupt response behavior that

[PATCH 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/ta