RE: [PATCH v1 00/21] Control coprocessor reset for AST2700

.97540-1-...@redhat.com/ QEMU version: https://github.com/qemu/qemu/commit/f96b157ebb93f94cd56ebbc99bc20982b8fd86ef Jamin > Jamin Lin (21): > hw/arm/aspeed_ast27x0-fc: Support VBootRom > hw/arm/ast27x0: Move SSP coprocessor initialization from machine to > SoC leve > hw/arm/ast2

[PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test

manually loading boot images and firmwares via `-device loader`. The vBootROM integrates boot sequencing for PSP, TSP, and SSP and sets up SCU configuration as part of its flow, enabling more realistic full-system testing without relying on console switching. Signed-off-by: Jamin Lin

[PATCH v1 14/21] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior

the real-world flow where the PSP controls TSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-tsp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 4c3b18695e..49a49604de 1006

[PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support

: Jul 17 2025 02:26:07 FW Version : git-f9eb0bb Signed-off-by: Jamin Lin --- pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/pc-bios/ast27x0_bootrom.bin b/pc-bios/ast27x0_bootrom.bin in

[PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers

functions and register bit layout as SSP, with logic selected by cpuid and distinct external reset sources. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 31 --- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc

[PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap

| 0x0200_ | | remap2 base| | | - SCU_148: target addr | | size: 32MB(SCU_154)| |---> |remap1 | |--| || Signed

[PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order

device realization order is explicitly managed: "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized. This ensures that PSP and SSP access a consistent SCU state, as expected by hardware. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw

[PATCH v1 21/21] docs: Add support vbootrom for ast2700fc

Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 41 -- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index bf18c56347..bc836e486f 100644 --- a/docs/system/arm/aspeed.rst +++ b

[PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP and ensure correct device realization order

ealization order is explicitly managed: "aspeed_soc_ast2700_tsp_realize()" is invoked after SRAM is initialized. This ensures that TSP’s access to shared SRAM functions correctly. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-tsp.c | 5 + hw/arm/aspeed_ast27x0.c |

[PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order

ealization order is explicitly managed: "aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized. This ensures that SSP’s access to shared SRAM functions correctly. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-ssp.c | 5 + hw/arm/aspeed_ast27x0

[PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap and update realization order

. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-tsp.c | 2 ++ hw/arm/aspeed_ast27x0.c | 9 + 3 files changed, 12 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index d628a189c1..83e07582d2 100644 --- a/include

[PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap

(SCU_194)| | | |--| || SCU VMState version remains at 3, as it was already bumped in a previous commit. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_scu.h | 1 + hw/arm/aspeed_ast27x0.c | 3 +++ hw/misc/aspeed_scu.c | 24 +++- 3 files changed, 27 i

[PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing

hange. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 40 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2d27eb1deb..9d67c5f631 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/h

[PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order

coprocessor realization. This allows SSP to reference the alias regions during its SDRAM setup. Additionally, the realization order comment has been updated to reflect the new DRAM dependency: coprocessors must now be realized after DRAM, SRAM, and SCU are all initialized. Signed-off-by: Jamin Lin

[PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP and ensure correct device realization order

device realization order is explicitly managed: "aspeed_soc_ast2700_tsp_realize()" is invoked after the SCU is initialized. This ensures that PSP and TSP access a consistent SCU state, as expected by hardware. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + h

[PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior

the real-world flow where the PSP controls SSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index fff95eac6a..b1dfbc4292 1006

[PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers

for the AST2700 SoC. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 94 1 file changed, 94 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 21a0d1ad5c..50f3f6ff17 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc

[PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP memory to SDRAM and use dram_container for remap support

ng "dram_container" makes it easier to manage aliases and remap logic. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-tsp.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 4e

[PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom

ASPEED_DEV_SPI_BOOT. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-fc.c | 75 ++ 1 file changed, 75 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 7087be4288..e2eee6183f 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm

[PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve

step for future commits that will support shared SCU, SRAM, and memory remap logic—specifically enabling PSP DRAM remap for SSP SDRAM access. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 27 +--- hw/arm/aspeed_ast27x0-fc.c | 30 ++ hw/arm

[PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support

g subregions at specific offsets. Using "dram_container" makes it easier to manage aliases and remap logic. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm

[PATCH v1 03/21] hw/arm/ast27x0: Move TSP coprocessor initialization from machine to SoC leve

mory remap handling across PSP, SSP, and TSP. Future commits will add memory remap mechanisms and tightly integrated SoC controller coordination. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 26 ++ hw/arm/aspeed_ast27x0-fc.c | 32 ++

[PATCH v1 00/21] Control coprocessor reset for AST2700

coprocessor reset via SCU registers. Jamin Lin (21): hw/arm/aspeed_ast27x0-fc: Support VBootRom hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve hw/arm/ast27x0: Move TSP coprocessor initialization from machine to SoC leve hw/arm/aspeed_ast27x0-ssp: Switch SSP

RE: [PATCH v1 00/18] Support AST2700 A1

Hi Cédric, > Subject: Re: [PATCH v1 00/18] Support AST2700 A1 > > Hello, > > >> Should we switch the alias to point to 'ast2700a1-evb' in QEMU 10.1.0 ? > >> and deprecate the A0 SoC and machine if it is no longer planned to > >> support them. > >> > > > > Sorry for the late reply and delay in pr

[PATCH v1] aspeed: Deprecate the ast2700a0-evb machine

The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin --- docs/about

RE: [PATCH v1 00/18] Support AST2700 A1

Hi Cédric > Subject: Re: [PATCH v1 00/18] Support AST2700 A1 > > Hi, > > On 1/31/25 08:34, Cédric Le Goater wrote: > > Hello Jamin, > > > > On 1/21/25 08:04, Jamin Lin wrote: > >> v1: > >>   1. Refactor INTC model to support both INTC0 and IN

RE: [PATCH v4] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly

gt; > Signed-off-by: Tan Siewert > > Could you please resend your R-b ? > > Thanks, > > C. > > Reviewed-by: Jamin Lin Thanks-Jamin > > > --- > > V4: > >- Fix mis-understanding of or operator in lock check [Tan] > >- Move

[PATCH v1 1/2] hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700

-boot/commit/94e5435504fb0df5c1bfd3fa284cdd6aaf9b Signed-off-by: Jamin Lin --- hw/misc/aspeed_sdmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index f04d9930dd..dff7cc362d 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_s

[PATCH v1 2/2] hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700

confirmed from an EVB register dump. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 4930e00fed..11d0739108 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -176,6 +176,7

[PATCH v1 0/2] Support the Frequency Counter Control register for AST2700

v1: - Skipping dram_init in u-boot for AST2700 - Support the Frequency Counter Control register for AST2700 Jamin Lin (2): hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700 hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700 hw/misc/aspeed_scu.c

RE: [PATCH v3] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly

s[AST2600_PROT_KEY2] = value; > +return; > +case AST2600_PROT_KEY2: > +s->regs[AST2600_PROT_KEY2] = (data == ASPEED_SCU_PROT_KEY) ? > 1 > + : 0; > return; > case AST2600_HW_STRAP1: > case AST2600_HW_STRAP2: > -- > 2.49.0 Reviewed-by: Jamin Lin Thanks-Jamin

RE: [PATCH v2] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly

> registers correctly > > Hi Tan, > > > Subject: [PATCH v2] hw/misc/aspeed_scu: Handle AST2600 protection key > > registers correctly > > > > The AST2600 SCU has two protection key registers (0x00 and 0x10) that > > both need to be unlocked. Each must be unlocked individually, but > > locking one

RE: [PATCH v2] hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly

Hi Tan, > Subject: [PATCH v2] hw/misc/aspeed_scu: Handle AST2600 protection key > registers correctly > > The AST2600 SCU has two protection key registers (0x00 and 0x10) that both > need to be unlocked. Each must be unlocked individually, but locking one will > lock both. > > This commit update

RE: [PATCH v3 00/28] Fix incorrect hash results on AST2700

Hi Cédric > Subject: Re: [PATCH v3 00/28] Fix incorrect hash results on AST2700 > > Hello Michael > > On 5/29/25 09:29, Michael Tokarev wrote: > > On 15.05.2025 11:09, Jamin Lin via wrote: > > > >> This patchset resolves incorrect hash results reported

[PATCH v2 0/3] Fix RAM size detection failure on BE hosts

v1: 1. Fix RAM size detection failure on BE hosts 2. INTC: Set impl.min_access_size to 4 Fix coding style v2: Fix review issue. Jamin Lin (3): hw/intc/aspeed: Set impl.min_access_size to 4 hw/intc/aspeed Fix coding style hw/arm/aspeed_ast27x0: Fix RAM size detection failure on

[PATCH v2 2/3] hw/intc/aspeed Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/intc/aspeed_intc.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 19f88853d8..5cd786dee6 100644 --- a/hw/intc

[PATCH v2 3/3] hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts

cit 32-bit little-endian write. - Updating the MemoryRegionOps to restrict access to exactly 4 bytes using .valid.{min,max}_access_size = 4 and .impl.min_access_size = 4. Signed-off-by: Jamin Lin Fixes: 7436db1 ("aspeed/soc: fix incorrect dram size for AST2700") --- hw/arm/aspeed_ast27x0.c | 10

[PATCH v2 1/3] hw/intc/aspeed: Set impl.min_access_size to 4

This patch explicitly sets ".impl.min_access_size = 4" to match the declared ".valid.min_access_size = 4", enforcing stricter access size checking and preventing inconsistent partial accesses to the interrupt controller registers. Signed-off-by: Jamin Lin Reviewed-by: Cédri

RE: [PATCH v1 3/3] hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts

Hi Cédric > Subject: Re: [PATCH v1 3/3] hw/arm/aspeed_ast27x0: Fix RAM size detection > failure on BE hosts > > On 5/20/25 09:35, Jamin Lin wrote: > > On big-endian hosts, the aspeed_ram_capacity_write() function > > previously passed the address of a 64-bit &qu

[PATCH v1 3/3] hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts

temporary "uint32_t le_data". - Updating the MemoryRegionOps to restrict access to exactly 4 bytes using .valid.{min,max}_access_size = 4 and .impl.min_access_size = 4. Signed-off-by: Jamin Lin Fixes: 7436db1 ("aspeed/soc: fix incorrect dram size for AST2700") --- hw/arm/aspeed

[PATCH v1 2/3] hw/intc/aspeed Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 19f88853d8..5cd786dee6 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc

[PATCH v1 1/3] hw/intc/aspeed: Set impl.min_access_size to 4

This patch explicitly sets ".impl.min_access_size = 4" to match the declared ".valid.min_access_size = 4", enforcing stricter access size checking and preventing inconsistent partial accesses to the interrupt controller registers. Signed-off-by: Jamin Lin --- hw/intc/aspeed_

[PATCH v1 0/3] Fix RAM size detection failure on BE hosts

v1: 1. Fix RAM size detection failure on BE hosts 2. INTC: Set impl.min_access_size to 4 Fix coding style Jamin Lin (3): hw/intc/aspeed: Set impl.min_access_size to 4 hw/intc/aspeed Fix coding style hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts hw/arm

RE: [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 A1

Hi Cédric > Subject: Re: [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 > A1 > > On 5/16/25 04:59, Jamin Lin wrote: > > Hi Cédric > > > >> > >> On a BE host, if I run an ast2700a0-evb machine : > >> >

RE: [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller

Hi Philippe, > Subject: Re: [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO > Controller > > On 9/3/25 14:51, Cédric Le Goater wrote: > > From: Jamin Lin > > > > Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. > > Added new regist

RE: [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 A1

Hi Cédric > > On a BE host, if I run an ast2700a0-evb machine : > > $ qemu-system-aarch64 -machine ast2700a0-evb ... > ... > U-Boot 2023.10-v00.05.06 (Mar 26 2025 - 05:59:26 +) > > SOC: AST2700-A0 > Model: AST2700 EVB > DRAM: 8 GiB (effective 0 Bytes) > > QEMU han

[PATCH v3 02/28] hw/misc/aspeed_hace: Improve readability and consistency in variable naming

Currently, users define multiple local variables within different if-statements. To improve readability and maintain consistency in variable naming, rename the variables accordingly. Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address. Signed-off-by: Jamin Li

[PATCH v3 26/28] test/qtest/hace: Support to test upper 32 bits of digest and source addresses

Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both

[PATCH v3 00/28] Fix incorrect hash results on AST2700

H values generated here should exactly match those computed on the host machine using sha shell commands, verifying both the correctness of the hardware-accelerated results and the functionality of the ast_crypto_engine. Jamin Lin (28): hw/misc/aspeed_hace: Remove unused code for better readabil

[PATCH v3 25/28] test/qtest/hace: Support 64-bit source and digest addresses for AST2700

Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI" registers to store upper 32 bits. Updated "write_regs" to handle 64-bit source and digest addresses. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/

[PATCH v3 19/28] test/qtest/hace: Specify explicit array sizes for test vectors and hash results

To enhance code readability and prevent potential buffer overflows or unintended size assumptions, this commit updates all fixed-size array declarations to use explicit array sizes. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 26 +- 1 file changed, 13

[PATCH v3 20/28] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations

ze to 0x3 (192KB). buffer_addr = src_addr + 0x1 digest_addr = src_addr + 0x40000 Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspee

[PATCH v3 13/28] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses

[7:0] - 4. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 3 +++ hw/misc/aspeed_hace.c | 31 ++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index f30d606559..9945b

[PATCH v3 07/28] hw/misc/aspeed_hace: Extract non-accumulation hash execution into helper function

To improve code readability and maintainability of do_hash_operation(), this commit introduces a new helper function: hash_execute_non_acc_mode(). The helper encapsulate the hashing logic for non-accumulation mode. No functional changes are introduced. Signed-off-by: Jamin Lin --- hw/misc

[PATCH v3 03/28] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang

always be set to ensure that the firmware receives an interrupt from the HACE module, preventing it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin Fixes: c5475b3 ("hw: Model ASPEED's Hash and Crypto Engine") --- hw/misc/aspeed_hace.c | 18 +--

[PATCH v3 27/28] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses

Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both

[PATCH v3 15/28] hw/misc/aspeed_hace: Add trace-events for better debugging

Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg", "trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode", and "trace_aspeed_hace_write" trace events. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 10 +

[PATCH v3 28/28] test/qtest/hace: Add tests for AST2700

address starts at "0x1207", and the DRAM start address is "0x4_". Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/ast2700-hace-test.c | 98 + tests/qtest/meson.build | 2 + 2 files changed, 100 insert

[PATCH v3 18/28] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases

-utils.c. All common APIs and test cases have been moved from aspeed_hace-test.c to aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs. As a result, these test cases can now be reused for AST2700 and future ASPEED SoC testing. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater

[PATCH v3 21/28] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model

Introduced SHA-384 test functions to verify hashing operations. Extended support for scatter-gather ("_sg") and accumulation ("_accum") tests. Updated test result vectors for SHA-384 validation. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 6 ++ tes

[PATCH v3 24/28] test/qtest/hace: Update source data and digest data type to 64-bit

addressing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 20 - tests/qtest/aspeed-hace-utils.c | 72 - 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h index

[PATCH v3 16/28] hw/misc/aspeed_hace: Support to dump plaintext and digest for better debugging

1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump. 2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vectors. 3. Introduced a new trace event: "aspeed_hace_hexdump". Signed-off-by: Jamin Lin -

[PATCH v3 12/28] hw/misc/aspeed_hace: Move register size to instance class and dynamically allocate regs

s accordingly. The VMState version was already bumped in a previous patch of this series, so no further version change is needed. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 5 +++-- hw/misc/aspeed_hace.c | 36 ++- 2 files changed, 22 insertion

[PATCH v3 09/28] hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function

urce hash buffer address. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 24 +--- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 33e13974fe..b3c3af51fa 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/asp

[PATCH v3 14/28] hw/misc/aspeed_hace: Support DMA 64 bits dram address

attribute and set it to true for the AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 17 - 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index

[PATCH v3 08/28] hw/misc/aspeed_hace: Extract accumulation-mode hash execution into helper function

with I/O vector unmapping. No functional changes are introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 74 --- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index c50e228cdf

[PATCH v3 22/28] test/qtest/hace: Add SHA-384 tests for AST2600

Introduced "test_sha384_ast2600" to validate SHA-384 hashing. Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification. Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation. Registered new test cases in "main" to ensure execut

[PATCH v3 23/28] test/qtest/hace: Add tests for AST1030

starts at "0x7e6d", and the SDRAM start address is "0x0". Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/aspeed_hace-test.c | 76 ++ 1 file changed, 76 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tes

[PATCH v3 10/28] hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper

logic and improve code readability. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 25 +++-- 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index b3c3af51fa..62649b5b27 100644 --- a/hw/misc/aspeed_hace.c +++ b

[PATCH v3 01/28] hw/misc/aspeed_hace: Remove unused code for better readability

. - Deleted "iov_cache" and "iov_count" from "AspeedHACEState". - Removed "reconstruct_iov" function and related logic. - Simplified "do_hash_operation" by eliminating redundant checks. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_

[PATCH v3 17/28] tests/qtest: Reorder aspeed test list

Reordered the aspeed test list to keep the alphabetical order. No functional changes in test behavior. Signed-off-by: Jamin Lin --- tests/qtest/meson.build | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index

[PATCH v3 04/28] hw/misc/aspeed_hace: Extract direct mode hash buffer setup into helper function

. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 42 -- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 1256926d22..42c6f29f82 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c

[PATCH v3 06/28] hw/misc/aspeed_hace: Extract digest write and iov unmap into helper function

introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 33 + 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 22eea62693..7da781f864 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc

[PATCH v3 05/28] hw/misc/aspeed_hace: Extract SG-mode hash buffer setup into helper function

detection. No functional changes are introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 111 -- 1 file changed, 63 insertions(+), 48 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 42c6f29f82..22eea62693 100644 --- a

[PATCH v3 11/28] hw/misc/aspeed_hace: Support accumulative mode for direct access mode

Check for padding and determine whether this is the final request. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 24 +--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 62649b5b27..049f732f99 100644 -

RE: [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits dram address.

Hi Cédric > > > > > >> The SG_LIST_ADDR_MASK needs an update though. AFAICT, it's bigger > > >> on AST2700. > > > > > > The value of SG_LIST_ADDR_MASK was wrong for AST2700, AST2600 and > > AST1030. > > > The correct value should be 0x7FF8. > > > Will create a new patch to fix it. > > > Please

RE: [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits dram address.

> Subject: RE: [PATCH v1 08/22] hw/misc/aspeed_hace: Support DMA 64 bits > dram address. > > Hi Cédric > > > > > > > > >> The SG_LIST_ADDR_MASK needs an update though. AFAICT, it's bigger > > > >> on AST2700. > > > > > > > > The value of SG_LIST_ADDR_MASK was wrong for AST2700, AST2600 and > > >

RE: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into helper functions for clarity

Hi Cédric > Subject: Re: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into > helper functions for clarity > > Hello Jamin, > > On 5/14/25 04:48, Jamin Lin wrote: > > Hi Cédric, > > > >> Subject: RE: [PATCH v2 05/25] hw/misc/aspeed_hace

RE: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into helper functions for clarity

t; Hello Jamin > > > > On 5/13/25 08:28, Jamin Lin wrote: > > > Refactor "do_hash_operation()" by extracting hash execution and > > > result handling into dedicated helper functions: > > > > > > - "hash_write_digest_an

RE: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into helper functions for clarity

Hi Cédric > Subject: Re: [PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into > helper functions for clarity > > Hello Jamin > > On 5/13/25 08:28, Jamin Lin wrote: > > Refactor "do_hash_operation()" by extracting hash execution and result > >

[PATCH v1] tests/qtest/aspeed_smc-test: Fix memory leaks

Link: https://patchwork.kernel.org/project/qemu-devel/patch/20250509175047.26066-1-faro...@suse.de/ Signed-off-by: Jamin Lin --- tests/qtest/aspeed_smc-test.c | 5 + 1 file changed, 5 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 4e1389385d

[PATCH v2 03/25] hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang

always be set to ensure that the firmware receives an interrupt from the HACE module, preventing it from getting stuck or repeatedly sending HASH commands. Signed-off-by: Jamin Lin Fixes: c5475b3 ("hw: Model ASPEED's Hash and Crypto Engine") --- hw/misc/aspeed_hace.c | 18 +--

[PATCH v2 01/25] hw/misc/aspeed_hace: Remove unused code for better readability

. - Deleted "iov_cache" and "iov_count" from "AspeedHACEState". - Removed "reconstruct_iov" function and related logic. - Simplified "do_hash_operation" by eliminating redundant checks. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_

[PATCH v2 15/25] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases

-utils.c. All common APIs and test cases have been moved from aspeed_hace-test.c to aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs. As a result, these test cases can now be reused for AST2700 and future ASPEED SoC testing. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater

[PATCH v2 18/25] test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model

Introduced SHA-384 test functions to verify hashing operations. Extended support for scatter-gather ("_sg") and accumulation ("_accum") tests. Updated test result vectors for SHA-384 validation. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 6 ++ tes

[PATCH v2 22/25] test/qtest/hace: Support 64-bit source and digest addresses for AST2700

Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI" registers to store upper 32 bits. Updated "write_regs" to handle 64-bit source and digest addresses. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/

[PATCH v2 21/25] test/qtest/hace: Update source data and digest data type to 64-bit

addressing. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.h | 20 - tests/qtest/aspeed-hace-utils.c | 72 - 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h index

[PATCH v2 10/25] hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses

[7:0] - 4. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 3 +++ hw/misc/aspeed_hace.c | 31 ++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index f30d606559..9945b

[PATCH v2 23/25] test/qtest/hace: Support to test upper 32 bits of digest and source addresses

Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both

[PATCH v2 24/25] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses

Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both

[PATCH v2 17/25] test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations

ze to 0x3 (192KB). buffer_addr = src_addr + 0x1 digest_addr = src_addr + 0x40000 Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspee

[PATCH v2 16/25] test/qtest/hace: Specify explicit array sizes for test vectors and hash results

To enhance code readability and prevent potential buffer overflows or unintended size assumptions, this commit updates all fixed-size array declarations to use explicit array sizes. Signed-off-by: Jamin Lin --- tests/qtest/aspeed-hace-utils.c | 26 +- 1 file changed, 13

[PATCH v2 20/25] test/qtest/hace: Add tests for AST1030

starts at "0x7e6d", and the SDRAM start address is "0x0". Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/aspeed_hace-test.c | 76 ++ 1 file changed, 76 insertions(+) diff --git a/tests/qtest/aspeed_hace-test.c b/tes

[PATCH v2 25/25] test/qtest/hace: Add tests for AST2700

address starts at "0x1207", and the DRAM start address is "0x4_". Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- tests/qtest/ast2700-hace-test.c | 98 + tests/qtest/meson.build | 2 + 2 files changed, 100 insert

[PATCH v2 19/25] test/qtest/hace: Add SHA-384 tests for AST2600

Introduced "test_sha384_ast2600" to validate SHA-384 hashing. Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification. Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation. Registered new test cases in "main" to ensure execut

[PATCH v2 14/25] tests/qtest: Reorder aspeed test list

Reordered the aspeed test list to keep the alphabetical order. No functional changes in test behavior. Signed-off-by: Jamin Lin --- tests/qtest/meson.build | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index

[PATCH v2 12/25] hw/misc/aspeed_hace: Add trace-events for better debugging

Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg", "trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode", and "trace_aspeed_hace_write" trace events. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 11

[PATCH v2 11/25] hw/misc/aspeed_hace: Support DMA 64 bits dram address

attribute and set it to true for the AST2700. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 17 - 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index

[PATCH v2 05/25] hw/misc/aspeed_hace: Split hash execution into helper functions for clarity

ne-shot (non-accumulated) hash operations. - "hash_execute_acc_mode()": Handles accumulated hashing, including update and finalize logic. No functional changes introduced. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 133 ++ 1 file

[PATCH v2 13/25] hw/misc/aspeed_hace: Support to dump plaintext and digest for better debugging

1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump. 2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vectors. 3. Introduced a new trace event: "aspeed_hace_hexdump". Signed-off-by: Jamin Lin -

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