Hi Richard,
On Sat, Apr 29, 2023 at 10:28:03AM +0100, Richard Henderson wrote:
> On 4/27/23 03:09, Jamie Iles wrote:
> > From: Jamie Iles
> >
> > The round-robin scheduler will iterate over the CPU list with an
> > assigned budget until the next timer expiry and may
nt enabled and no hangs.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Peter Maydell
Signed-off-by: Jamie Iles
---
accel/tcg/tcg-accel-ops-icount.c | 17 +--
accel/tcg/tcg-accel-ops-icount.h | 3 ++-
accel/tcg/tcg-accel-ops-rr.c | 37 +++-
3 files c
From: Jamie Iles
The round-robin scheduler will iterate over the CPU list with an
assigned budget until the next timer expiry and may exit early because
of a TB exit. This is fine under normal operation but with icount
enabled and SMP it is possible for a CPU to be starved of run time and
the
Expose qemu_cpu_list_lock globally so that we can use
WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths
now and in future.
Signed-off-by: Jamie Iles
---
cpus-common.c | 2 +-
include/exec/cpu-common.h | 1 +
linux-user/elfload.c | 12
Hi Richard,
On Mon, Apr 24, 2023 at 02:06:18PM +0100, Richard Henderson wrote:
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
>
> On 4/24/23 12:29, Jamie Iles wrote:
> > +/*
> > + * Calc
nt enabled and no hangs.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Peter Maydell
Signed-off-by: Jamie Iles
---
Changes in v2:
- Rename icount_cpu_timeslice to icount_percpu_budget
- Add a clarifying comment about caching to rr_cpu_count()
accel/tcg/tcg-accel-ops-ico
nt enabled and no hangs.
Signed-off-by: Jamie Iles
---
accel/tcg/tcg-accel-ops-icount.c | 16 ++--
accel/tcg/tcg-accel-ops-icount.h | 3 ++-
accel/tcg/tcg-accel-ops-rr.c | 26 +-
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/tcg
Hi Philippe,
On Thu, Nov 11, 2021 at 05:04:56PM +, Jamie Iles wrote:
> On Thu, Nov 11, 2021 at 04:55:35PM +0100, Philippe Mathieu-Daudé wrote:
> > On 11/11/21 16:43, Philippe Mathieu-Daudé wrote:
> > > On 11/11/21 16:36, Jamie Iles wrote:
> > >> Hi Philippe,
>
On Thu, Nov 11, 2021 at 04:55:35PM +0100, Philippe Mathieu-Daudé wrote:
> On 11/11/21 16:43, Philippe Mathieu-Daudé wrote:
> > On 11/11/21 16:36, Jamie Iles wrote:
> >> Hi Philippe,
> >>
> >> On Thu, Nov 11, 2021 at 03:55:48PM +0100, Philippe Mathieu-Daudé wrot
Hi Philippe,
On Thu, Nov 11, 2021 at 03:55:48PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Jamie,
>
> On 11/11/21 15:11, Jamie Iles wrote:
> > On Linux, read() will only ever read a maximum of 0x7000 bytes
> > regardless of what is asked. If the file is larger than 0x7
On Linux, read() will only ever read a maximum of 0x7000 bytes
regardless of what is asked. If the file is larger than 0x7000
bytes the read will need to be broken up into multiple chunks.
Cc: Luc Michel
Signed-off-by: Jamie Iles
---
hw/core/loader.c | 40
Various loader functions return an int which limits images to 2GB which
is fine for things like a BIOS/kernel image, but if we want to be able
to load memory images or large ramdisks then any file over 2GB would
silently fail to load.
Cc: Luc Michel
Signed-off-by: Jamie Iles
---
hw/arm
type") to cover more of the generic loader.
Jamie Iles (2):
hw/core/loader: return image sizes as ssize_t
hw/core/loader: workaround read() size limit.
hw/arm/armv7m.c | 2 +-
hw/arm/boot.c| 8 +--
hw/core/generic-loader.c | 2 +-
hw/core/loader.c
Now that raise_exception_ra restores the state before raising the
exception we can use restore_exception_ra to perform the state restore +
exception raising without clobbering the PC/condbits.
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/m_helper.c | 5
now redundant open coded raise_exception_ra from MTE and stack
limit exception handling
Jamie Iles (4):
target/arm: fix missing exception class
target/arm: fold do_raise_exception into raise_exception
target/arm: use raise_exception_ra for MTE check failure
target/arm: use
Now that raise_exception_ra restores the state before raising the
exception we can use restore_exception_ra to perform the state restore +
exception raising without clobbering the syndrome.
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/mte_helper.c | 11
lpers")
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/op_helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index efcb60099277..078ed74ab962 100644
--- a/target/arm/op_help
Now that there are no other users of do_raise_exception, fold it into
raise_exception.
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/op_helper.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/arm/op_helper.c b/target
also makes it possible for real CPU models
to use the impdef algorithm for improved performance by setting
pauth-impdef=on on the command line.
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
Following Richard's suggestion to make impdef selectable for all CPUs
Hi Peter,
On Mon, May 24, 2021 at 10:41:58AM +0100, Peter Maydell wrote:
> On Mon, 24 May 2021 at 09:42, Jamie Iles wrote:
> >
> > The DAIF and PAC checks used raise_exception_ra to raise an exception
> > and unwind CPU state but raise_exception_ra is currently designed
("target/arm: Add PAuth helpers")
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/helper-a64.c | 12 +++-
target/arm/pauth_helper.c | 4 +++-
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/
them unless there is a property registered that can
disable them.
Cc: Richard Henderson
Cc: Peter Maydell
Signed-off-by: Jamie Iles
---
target/arm/cpu64.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cp
Commit c62f6d1 (monitor: fix build breakage with --disable-vnc)
conditionalised some VNC setup code but left an unused variable. Move
the variable into the conditional code to fix the build breakage.
Cc: Luiz Capitulino
Cc: Markus Armbruster
Signed-off-by: Jamie Iles
---
monitor.c |2
On Wed, Jul 20, 2011 at 03:35:19PM +0100, Peter Maydell wrote:
> On 19 July 2011 13:32, Jamie Iles wrote:
> > Add support for v6K ARM1176JZF-S. This core includes the VA<->PA
> > translation capability and security extensions.
>
> > +static uint32_t arm1176_cp15
On Wed, Jul 20, 2011 at 04:59:29PM +0100, Peter Maydell wrote:
> On 20 July 2011 16:36, Jamie Iles wrote:
> > On Wed, Jul 20, 2011 at 03:35:19PM +0100, Peter Maydell wrote:
> >> On 19 July 2011 13:32, Jamie Iles wrote:
> >> > Add support for v6K ARM1176JZF-S.
Add support for v6K ARM1176JZF-S. This core includes the VA<->PA
translation capability and security extensions.
v2: Model the version with the VFP
Cc: Peter Maydell
Cc: Paul Brook
Cc: Aurelien Jarno
Signed-off-by: Jamie Iles
---
target-arm/cpu.h|1 +
target-arm/helper.c
The VMSAv7 remapping and access permissions were introduced in ARMv6K
and not ARMv7.
Cc: Peter Maydell
Cc: Aurelien Jarno
Cc: Paul Brook
Signed-off-by: Jamie Iles
---
target-arm/helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target
Add support for v6K ARM1176JZ-S. This core includes the VA<->PA
translation capability and security extensions.
Cc: Peter Maydell
Cc: Paul Brook
Cc: Aurelien Jarno
Signed-off-by: Jamie Iles
---
target-arm/cpu.h|1 +
target-arm/helper.c | 19 +++
2 files chang
On Wed, Jun 22, 2011 at 05:01:30PM +0100, Peter Maydell wrote:
> On 22 June 2011 16:45, Jamie Iles wrote:
> > On Wed, Jun 22, 2011 at 10:40:12AM +0100, Peter Maydell wrote:
> >> Mostly what I'd like is for the actual code implementing things to
> >> be gated on a
On Wed, Jun 22, 2011 at 10:40:12AM +0100, Peter Maydell wrote:
> On 22 June 2011 00:42, Jamie Iles wrote:
> > On 21 June 2011 23:13, Peter Maydell wrote:
> >> Ah yes, sorry, I misread the TRM there. So it does have those, it's
> >> just the SEV/WFI/WFE it i
On 21 June 2011 23:13, Peter Maydell wrote:
> On 21 June 2011 17:13, Jamie Iles wrote:
>> Hi Peter,
>>
>> On Tue, Jun 21, 2011 at 04:43:44PM +0100, Peter Maydell wrote:
>>> On 21 June 2011 13:55, Jamie Iles wrote:
>>> > + case ARM_CPU
Hi Peter,
On Tue, Jun 21, 2011 at 04:43:44PM +0100, Peter Maydell wrote:
> On 21 June 2011 13:55, Jamie Iles wrote:
> > + case ARM_CPUID_ARM1176:
> > + set_feature(env, ARM_FEATURE_V4T);
> > + set_feature(env, ARM_FEATURE_V5);
> > + set_
Add support for the ARM1176JZ-s cores. The ARM1176JZ-s is a v6K core
but uses the v7 VMSA for remapping and access permissions and there is
no way to identify these VMSA extensions from the cpuid feature
registers.
Cc: Paul Brook
Cc: Aurelien Jarno
Signed-off-by: Jamie Iles
---
target-arm
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