I agree with this implementation. Though WFI seems make no sense for a
userspace program, we should not have assumption that the userspace
program will not use this instruction.
It seems ARM manual does not defined the implementation of function
EnterLowPowerState(); However, before executing thi
cmd： ~/qemu-5.1.0/arm-linux-user/qemu-arm ~/test2
QEMU version: qemu-arm version 5.1.0
Sorry that I didn't test it on the latest version of QEMU.
** Attachment added: "test2"
https://bugs.launchpad.net/qemu/+bug/1926759/+attachment/5493873/+files/test2
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Public bug reported:
Hi
I refer to the WFI instruction. The bytecode is 0xe320f003. After the
execution, qemu exit with the following crash log.
qemu: unhandled CPU exception 0x10001 - aborting
R00=0001 R01=40800b34 R02=40800b3c R03=000102ec
R04=00010a28 R05=00010158 R06=00087460 R07=000101
Hi
Thanks for your reply. I don't think return false is the right behavior
here. H is related to decoding rather than encoding phase. The value of
symbol *H* should not be used to check whether the (encoding) pattern is
matched or not. In other words, whatever value H is, if the bytecode
meet the
Hi
I still feel QEMU's implementation is not right. Could you please check
it again.
According to https://developer.arm.com/documentation/ddi0406/c
/Application-Level-Architecture/Instruction-Details/Alphabetical-list-
of-instructions/BL--BLX--immediate-?lang=en
The encoding T2 for BLX is below:
Public bug reported:
Hi
I refer to the instruction BLX imm (T2 encoding) in ARMv7 (Thumb mode).
0 S imm10H 11 J1 0 J2 imm10L H
if H == '1' then UNDEFINED;
I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 =
SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
targetInstrSet = InstrSet_A32;
if InITB
We just test the patched version. It looks well. Now QEMU would raise
SEGILL signals, which should be the right behavior.
We are not checking should-UNDEF cases in particular. This is a case we
observed and checked manually when doing a research project with QEMU.
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Public bug reported:
Hi
It seems that QEMU does not have a proper check on the STR instruction
in Thumb32 mode.
Specifically, the machine code is 0xf84f0ddd, which is 0b 1000 0100
1101 1101 1101.
This is an STR (immediate, Thumb) instruction with a T4 encoding scheme.
The symbol
Public bug reported:
Hi
I refer to the implementation of exclusive monitor in ARM32. For
instruction like STREX Rx,Ry,[Rz], we need to check whether the address
[Rz] is in exclusive state. If not, we set the value Rx as 1 without
doing the store operation. However, I noticed that QEMU will not ch
Thanks for confirmation.
Btw: I was wondering why the fix will only apply to system mode rather
than user-only mode. Unaligned data access is not permitted in user
level programs, either.
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Public bug reported:
hi
According to the ARM documentation, there are alignment requirements of
load/store instructions. Alignment fault should be raised if the
alignment check is failed. However, it seems that QEMU doesn't implement
this, which is against the documentation of ARM. For example,
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