so can't be represented
> by explicit entries in the map.
> - Updated a couple of patch descriptions to provide answers to questions
> Eric raised.
I also tested the cxl/next kernel; it boots fine with CXL devices.
Tested-by: Itaru Kitayama
>
> v16:
> - Mostly addit
ntinues to work.
>
> Tested-by: Itaru Kitayama
> Reviewed-by: Eric Auger
> Signed-off-by: Jonathan Cameron
>
> ---
> v17: Tag and small fix for patch description (Eric).
> ---
> tests/qtest/cxl-test.c | 58 -
> tests/qt
inue to work.
>
> Tested-by: Itaru Kitayama
> Signed-off-by: Jonathan Cameron
>
> ---
> v16: Update to bring improvements made to other tests (Peter Maydell).
> I'd failed to notice when rebasing this over time that the
> other tests had undergone various improvm
a sufficient
> change to trigger dropping tags. (Zhijian Li)
> - A few other minor tweaks.
> - TLB issue mentioned in v14 now fixed upstream so dropped reference
> in this cover letter.
>
> Thanks to Itaru Kitayama and Zhijian Li for testing + reviews.
>
> Updated cover l
ONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
> []) + \
>(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) +
> \
>(config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \
> + qtests_cxl +
>\
>['arm-cpu-features',
> 'numa-test',
> 'boot-serial-test',
V15 is applied cleanly using b4 on top of today's master.
$ meson test qtest-aarch64/cxl-test
ninja: Entering directory `/home/realm/projects/qemu/build'
[1/8] Generating qemu-version.h with a custom command (wrapped by meson to
capture output)
1/1 qemu:qtest+qtest-aarch64 / qtest-aarch64/cxl-testOK
0.21s 1 subtests passed
Ok: 1
Expected Fail: 0
Fail: 0
Unexpected Pass:0
Skipped:0
Timeout:0
Tested-by: Itaru Kitayama
Thanks,
Itaru
> --
> 2.48.1
>
+ b/include/hw/cxl/cxl.h
> @@ -46,7 +46,6 @@ typedef struct CXLState {
> bool is_enabled;
> MemoryRegion host_mr;
> unsigned int next_mr_idx;
> -GList *fixed_windows;
> CXLFixedMemoryWindowOptionsList *cfmw_list;
> } CXLState;
With this one line removed on top of v14
needs additional patches not yet ready for upstream. The challenge
> is interleave - and the solution is don't interleave if you want to run
> with KVM.
Series applied cleanly on top of today's QEMU. And I confirm that
qtest-aarch64/cxl-test passes the test as it should and ndctl cxl
Hi Jonathan,
On Wed, May 28, 2025 at 12:07:21PM +0100, Jonathan Cameron wrote:
> v14: Simplifications suggeseted by Itaru (and some extra simplifications
> that became apparent) and gather tags.
> See individual patches for more information.
I think the suggestion was made by Zhi jian o
> On May 22, 2025, at 2:52, Jonathan Cameron
> wrote:
>
> On Wed, 21 May 2025 16:38:10 +0900
> Itaru Kitayama wrote:
>
>>> On May 19, 2025, at 21:54, Jonathan Cameron
>>> wrote:
>>>
>>> On Thu, 15 May 2025 18:04:18 +0900
>>&
> On May 19, 2025, at 21:54, Jonathan Cameron
> wrote:
>
> On Thu, 15 May 2025 18:04:18 +0900
> Itaru Kitayama wrote:
>
>>> On May 13, 2025, at 20:14, Jonathan Cameron
>>> wrote:
>>>
>>> Add a single complex case for aarch64 virt mac
Jonathan,
> On May 19, 2025, at 21:54, Jonathan Cameron
> wrote:
>
> On Thu, 15 May 2025 18:04:18 +0900
> Itaru Kitayama wrote:
>
>>> On May 13, 2025, at 20:14, Jonathan Cameron
>>> wrote:
>>>
>>> Add a single complex case
> On May 16, 2025, at 11:30, Itaru Kitayama wrote:
>
> Hi Jonathan,
>
>> On May 13, 2025, at 20:14, Jonathan Cameron
>> wrote:
>>
>> V13:
>> - Make CXL fixed memory windows sysbus devices.
>> IIRC this was requested by Peter in one of the
Hi Jonathan,
> On May 13, 2025, at 20:14, Jonathan Cameron
> wrote:
>
> V13:
> - Make CXL fixed memory windows sysbus devices.
> IIRC this was requested by Peter in one of the reviews a long time back
> but at the time the motivation was less strong than it becomes with some
> WiP patches fo
fig_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
> []) + \
> (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \
> + qtests_cxl +
>\
> ['arm-cpu-features',
>'numa-test',
>'boot-serial-test',
> --
> 2.43.0
>
~/projects/qemu/build$ meson test qtest-aarch64/cxl-test
ninja: Entering directory `/home/realm/projects/qemu/build'
[1/8] Generating qemu-version.h with a custom command (wrapped by meson to
capture output)
1/1 qemu:qtest+qtest-aarch64 / qtest-aarch64/cxl-testOK
0.17s 1 subtests passed
Ok: 1
Expected Fail: 0
Fail: 0
Unexpected Pass:0
Skipped:0
Timeout:0
Tested-by: Itaru Kitayama mailto:itaru.kitay...@fujitsu.com>>
Jonathan, would you push your branch this series applied? I manually applied
your series no issues though.
> On Feb 4, 2025, at 18:29, Jonathan Cameron
> wrote:
>
> On Tue, 4 Feb 2025 14:16:19 +0900
> Itaru Kitayama wrote:
>
>> Jonathan,
>>
>>> On Feb 4, 2025, at 2:30, Jonathan Cameron
>>> wrote:
>>>
>>> Add a single c
Jonathan,
> On Feb 4, 2025, at 2:30, Jonathan Cameron wrote:
>
> Add a single complex case for aarch64 virt machine.
> Given existing much more comprehensive tests for x86 cover the
> common functionality, a single test should be enough to verify
> that the aarch64 part continue to work.
>
> Si
> On Jan 30, 2025, at 2:16, Jonathan Cameron
> wrote:
>
> On Wed, 29 Jan 2025 10:14:34 +0900
> Itaru Kitayama wrote:
>
>>> On Jan 22, 2025, at 23:07, Jonathan Cameron
>>> wrote:
>>>
>>> On Fri, 17 Jan 2025 09:43:11 +
>>>
> On Jan 22, 2025, at 23:07, Jonathan Cameron
> wrote:
>
> On Fri, 17 Jan 2025 09:43:11 +
> Jonathan Cameron via wrote:
>
>> On Fri, 17 Jan 2025 10:13:41 +0900
>> Itaru Kitayama wrote:
>>
>>>> On Jan 16, 2025, at 19:58, Jonathan Cameron
> On Jan 16, 2025, at 19:58, Jonathan Cameron
> wrote:
>
> On Thu, 16 Jan 2025 15:04:53 +0900
> Itaru Kitayama wrote:
>
>> Hi Jonathan,
>>
>>> On Jan 14, 2025, at 19:26, Jonathan Cameron
>>> wrote:
>>>
>>> On Tue,
> On Jan 16, 2025, at 19:58, Jonathan Cameron
> wrote:
>
> On Thu, 16 Jan 2025 15:04:53 +0900
> Itaru Kitayama wrote:
>
>> Hi Jonathan,
>>
>>> On Jan 14, 2025, at 19:26, Jonathan Cameron
>>> wrote:
>>>
>>> On Tue,
Hi Jonathan,
> On Jan 14, 2025, at 19:26, Jonathan Cameron
> wrote:
>
> On Tue, 14 Jan 2025 12:03:03 +0900
> Itaru Kitayama wrote:
>
>> Hi Jonathan,
>>
>>> On Jan 10, 2025, at 21:31, Jonathan Cameron
>>> wrote:
>>>
>>>
Hi Jonathan,
> On Jan 10, 2025, at 21:31, Jonathan Cameron
> wrote:
>
> On Fri, 10 Jan 2025 09:20:54 +
> "Zhijian Li (Fujitsu)" via wrote:
>
>> On 10/01/2025 13:29, Itaru Kitayama wrote:
>>> Hi,
>>> Is anybody working on the CXL emul
Hi,
Is anybody working on the CXL emulation on aarch64?
If there’s a WIP branch, a pointer would be appreciated.
Itaru.
Hi Jean,
> On Nov 21, 2024, at 19:00, Jean-Philippe Brucker
> wrote:
>
> Hi Itaru,
>
> On Thu, Nov 21, 2024 at 02:34:24PM +0900, Itaru Kitayama wrote:
>> Hi Jean, Mathieu,
>>
>> I’ve been using you guys’ ccs/v3 QEMU for some time to bring up an Realm
&g
Hi Daniel,
> On Nov 21, 2024, at 18:58, Daniel P. Berrangé wrote:
>
> On Thu, Nov 21, 2024 at 06:55:18PM +0900, Itaru Kitayama wrote:
>>
>>
>>> On Nov 21, 2024, at 18:53, Daniel P. Berrangé wrote:
>>>
>>> On Thu, Nov 21, 2024 at 02:34:24PM +0
> On Nov 21, 2024, at 18:53, Daniel P. Berrangé wrote:
>
> On Thu, Nov 21, 2024 at 02:34:24PM +0900, Itaru Kitayama wrote:
>> Hi Jean, Mathieu,
>>
>> I’ve been using you guys’ ccs/v3 QEMU for some time to bring
>> up an Realm instance without a major iss
Hi Jean, Mathieu,
I’ve been using you guys’ ccs/v3 QEMU for some time to bring up an Realm
instance without a major issue, and as a one who is making changes libvirt to
support CCA, I wonder if you could merge the v3 local changes under qap dir
first so I can query the feature from libvirt?
Th
Hi,
I’ve been looking at the libvirt code to add Arm’s CCA support for some time
and I am wondering how QEMU folk want to implement the CCA query command. Any
pointer would be appreciated.
Thanks,
Itaru.
> On Jul 31, 2024, at 19:34, Daniel P. Berrangé wrote:
>
> On Wed, Jul 31, 2024 at 11:29:01AM +0100, Peter Maydell wrote:
>> On Wed, 31 Jul 2024 at 10:52, Alex Bennée wrote:
>>> You then need to manually strip out all the various chardevs for libvirt
>>> control sockets and you can an equival
Hi Alex,
> On Jul 30, 2024, at 22:25, Alex Bennée wrote:
>
> Itaru Kitayama writes:
>
>> Hi,
>>
>> Executing virt-install with the following options:
>>
>> sudo virt-install --machine=virt --arch=aarch64 --name=test8 --disk
>> path=/var/li
Hi,
Executing virt-install with the following options:
sudo virt-install --machine=virt --arch=aarch64 --name=test8 --disk
path=/var/lib/libvirt/images/jammy.qcow2,format=qcow2,device=disk,bus=virtio,cache=none
--memory=2048 --vcpu=1 --nographic --check all=off --features acpi=off
--import --o
Hi Jean,
> On May 31, 2024, at 19:21, Jean-Philippe Brucker
> wrote:
>
> Hi Itaru,
>
> On Fri, May 31, 2024 at 10:57:13AM +0100, Peter Maydell wrote:
>> On Fri, 31 May 2024 at 05:20, Itaru Kitayama
>> wrote:
>>>
>>>
>>>
>>&g
> On May 30, 2024, at 22:30, Philippe Mathieu-Daudé wrote:
>
> Cc'ing more developers
>
> On 30/5/24 06:30, Itaru Kitayama wrote:
>> Hi,
>> When I see a Realm VM creation fails with:
>> Unexpected error in rme_configure_one() at ../target/arm/kvm-
Hi,
When I see a Realm VM creation fails with:
Unexpected error in rme_configure_one() at ../target/arm/kvm-rme.c:159:
qemu-system-aarch64: RME: failed to configure SVE: Invalid argument
test.sh: line 8: 2502 Aborted qemu-system-aarch64 -M
'virt,acpi=off,gic-version=3' -cpu host
Doesn’t ‘max’ support being there mean we are supposed to support various
types of CPUs on the SBSA board?
On Fri, May 20, 2022 at 18:00 Peter Maydell
wrote:
> On Fri, 20 May 2022 at 09:46, Itaru Kitayama
> wrote:
> >
> > In target/arm/cpu64.c, CPU init function for A64FX
If Leif can jump in that’d be great.
On Fri, May 20, 2022 at 18:31 Itaru Kitayama
wrote:
> I’ve verified only a57 and a72 boot on sbsa ref board, but not N1 and
> ‘max’. As I said, I’ll try to figure out how CPU init is done in QEMU for
> those not working CPU types.
>
> On Fri,
I’ve verified only a57 and a72 boot on sbsa ref board, but not N1 and
‘max’. As I said, I’ll try to figure out how CPU init is done in QEMU for
those not working CPU types.
On Fri, May 20, 2022 at 18:27 Peter Maydell
wrote:
> On Fri, 20 May 2022 at 10:02, Itaru Kitayama
> wrote:
>
By calling a57’s CPU init function inside the max’s, I can bring up the
sbsa-ref board with the latest kernel. I’ll try to patch a64’s unit
function with Shuichiro next week.
On Fri, May 20, 2022 at 17:57 Peter Maydell
wrote:
> On Mon, 16 May 2022 at 02:58, Itaru Kitayama
> wrote:
> &
In target/arm/cpu64.c, CPU init function for A64FX is there, add this
CPU to the sbsa-ref board.
Signed-off-by: Itaru Kitayama
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 4bb444684f..a7d27b2e55 100644
--- a/hw/arm/sbsa
With the latest, manually built TF-A, I was able to boot a72, but not
max. Since `max` type is supported by TF-A, I think it might be
a Qemu issue.
On Mon, May 16, 2022 at 8:21 AM Itaru Kitayama wrote:
>
> Leif,
>
> I've so far only booted sbsa-ref with cortex-a57, is thi
Leif,
I've so far only booted sbsa-ref with cortex-a57, is this only CPU
type supported by the board? I'm using TF-A's latest branch, but the
PLAT=qemu_sbsa is at this moment, kind of outdated.
Itaru.
Thanks Richard I’ll look into it.
On Sat, May 14, 2022 at 0:03 Richard Henderson
wrote:
> On 5/12/22 22:59, Itaru Kitayama wrote:
> > Richard,
> > I'm wondering what options you use to bring up sbsa board with
> neoverse-n1
> > as I am only able to do it with c
Richard,
I'm wondering what options you use to bring up sbsa board with neoverse-n1
as I am only able to do it with cortex-a57, no other CPU types works.
Itaru.
Peter,
I’ll talk with Shuichiro this coming Monday (here most of us on vacation),
and get back to you.
Itaru.
On Sat, May 7, 2022 at 1:34 Peter Maydell wrote:
> On Fri, 6 May 2022 at 17:21, Peter Maydell
> wrote:
> >
> > Make the GICv3 set its number of bits of physical priority from the
> > i
On Tue, Apr 12, 2022 at 0:22 Alex Bennée wrote:
>
> Itaru Kitayama writes:
>
> > Good point; however per the SBSA specification, DEN0029F, there's the
> > PE architecture requirement at
> > each level from 1 to 7, so now I am wondering whether supporting
> &
7;
is there, but does not boot.
Itaru.
On Sat, Apr 9, 2022 at 12:04 AM Peter Maydell wrote:
>
> On Fri, 8 Apr 2022 at 15:59, Itaru Kitayama wrote:
> > I'd like to add a64fx cpu to the sbsa-ref board, if there's a quick and
> > dirty
> > way of completing that,
Hi,
I'd like to add a64fx cpu to the sbsa-ref board, if there's a quick and dirty
way of completing that, advice from the maintainers is greatly appreciated.
Thanks,
Itaru.
Hi Andre,
I've verified tests you proposed to the lists finish without an
issue with the kvm-arm-for-4.9-rc6 kernel.
Itaru
I am seeing the same:
# qemu-sparc64-static -version
qemu-sparc64 version 2.1.50, Copyright (c) 2003-2008 Fabrice Bellard
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1254828
Title:
qemu-sparc64-
The recent upstream highbank kernel uses smc to enable its L2 cache,
but on a qemu virt machine
it is not supported yet. Is it likely supported by qemu soon? What is
the time frame for that?
If support can not be expected any time soon, how do we work around
the issue? I have been using
qemu-linar
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