RE: [PATCH 00/11 v2] RISC-V: support CLIC v0.9 specification

been verified to match the Cirrus Logic silicon (PRV_M only), which is based upon the Pulp implementation [4] as of June 2023. How can I help move this forward to get it merged into the mainline? Thank you, Ian Brockbank C.Eng. Senior Staff Software Engineer Cirrus Logic | cirrus.com | t: +44 131

[PATCH 04/11 v2] target/riscv: Update CSR xie in CLIC mode

From: Ian Brockbank The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c

[PATCH 05/11 v2] target/riscv: Update CSR xip in CLIC mode

From: Ian Brockbank The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv

[PATCH 06/11 v2] target/riscv: Update CSR xtvec in CLIC mode

From: Ian Brockbank The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv

[PATCH 09/11 v2] target/riscv: Update interrupt return in CLIC mode

From: Ian Brockbank When a vectored interrupt is selected and serviced, the hardware will automatically clear the corresponding pending bit in edge-triggered mode. This may lead to a lower privilege interrupt pending forever. Therefore when interrupts return, pull a pending interrupt to service

[PATCH 08/11 v2] target/riscv: Update interrupt handling in CLIC mode

From: Ian Brockbank Decode CLIC interrupt information from exccode, includes interrupt privilege mode, interrupt level, and irq number. Then update CSRs xcause, xstatus, xepc, xintstatus and jump to correct PC according to the CLIC specification. Signed-off-by: LIU Zhiwei Signed-off-by: Ian

[PATCH 07/11 v2] target/riscv: Update CSR xnxti in CLIC mode

From: Ian Brockbank The CSR can be used by software to service the next horizontal interrupt when it has greater level than the saved interrupt context (held in xcause`.pil`) and greater level than the interrupt threshold of the corresponding privilege mode, Signed-off-by: LIU Zhiwei Signed

[PATCH 03/11 v2] hw/intc: Add CLIC device

From: Ian Brockbank The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow users to optimize each interrupt for either faster response or smaller code size

[PATCH 11/11 v2] tests: add riscv clic qtest case and a function in qtest

and detect the interrupt, qtest has also been updated to allow both an input and an output GPIO to be intercepted. Signed-off-by: Troy Song Signed-off-by: Ian Brockbank --- hw/intc/riscv_clic.c|4 + include/sysemu/qtest.h |2 + system/qtest.c | 72

[PATCH 10/11 v2] hw/riscv: add CLIC into virt machine

Signed-off-by: Ian Brockbank --- hw/riscv/virt.c | 235 +++- include/hw/riscv/virt.h | 35 ++ 2 files changed, 267 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cef41c150a..68d614ad5c 100644 --- a/hw/riscv

[PATCH 02/11 v2] target/riscv: Update CSR xintthresh in CLIC mode

From: Ian Brockbank The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: Ian Brockbank

[PATCH 01/11 v2] target/riscv: Add CLIC CSR mintstatus

From: Ian Brockbank CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: Ian Brockbank Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 3 +++ target/riscv

[PATCH 00/11 v2] RISC-V: support CLIC v0.9 specification

ve/riscv-qemu/tree/sifive-clic. [3] RFC Patch submission by Liu Zhiwei: https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html [4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic Ian Brockbank (11): target/riscv: Add CLIC CSR mintstatus target/riscv: Update CS

RE: [PATCH 00/11] RISC-V: support CLIC v0.9 specification

Apologies. Please ignore this patchset. Something seems to have gone wrong during the preparation and merge to current; I am working on a replacement, and will send v2 once I am happy with it. Ian Brockbank C.Eng. Senior Staff Software Engineer Cirrus Logic | cirrus.com | t: +44 131 272 7145

[PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

From: Ian Brockbank The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv

[PATCH 07/11] target/riscv: Update CSR xnxti in CLIC mode

From: Ian Brockbank The CSR can be used by software to service the next horizontal interrupt when it has greater level than the saved interrupt context (held in xcause`.pil`) and greater level than the interrupt threshold of the corresponding privilege mode, Signed-off-by: LIU Zhiwei Signed

[PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

From: Ian Brockbank The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv

[PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

From: Ian Brockbank The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c

[PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

From: Ian Brockbank CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: Ian Brockbank Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 3 +++ target/riscv

[PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

From: Ian Brockbank The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: Ian Brockbank

[PATCH 03/11] hw/intc: Add CLIC device

From: Ian Brockbank The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow users to optimize each interrupt for either faster response or smaller code size

[PATCH 00/11] RISC-V: support CLIC v0.9 specification

work: https://github.com/sifive/riscv-qemu/tree/sifive-clic. [3] RFC Patch submission by Liu Zhiwei: https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html [4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic Ian Brockbank (11): target/riscv: Add CLIC CSR mintstatus