[PATCH v3 2/2] hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype

This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing Signed-off-by: Yang Wang Signed-off-by: Yu H

[PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source, high-performance RISC-V processor. More details can be found at: https://github.com/OpenXiangShan/XiangShan Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized based on four RISC-V specifications: Volume

[PATCH v2 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU

Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source, high-performance RISC-V processor. More details can be found at: https://github.com/OpenXiangShan/XiangShan Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized based on four RISC-V specifications: Volume

[PATCH v1 2/2] hw/riscv: initial support for BOSC's Xiangshan Kunminghu SoC

This implementation provides emulation for the Xiangshan Kunminghu SoC, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Please note the following parameters when running the Xiangshan Kunminghu machine: 1.`-m`: C

[PATCH v1 1/2] target/riscv: add BOSC's Xiangshan Kunminghu CPU

Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source high-performance RISC-V processor. More details can be found at https://github.com/OpenXiangShan/XiangShan Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are categorized based on four RISC-V specifications: Volume I

[PATCH v2] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking

curacy, rather than the masked value. Signed-off-by: Huang Borong Reviewed-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 4866649115..0974c6a5db 100644 --- a/hw/intc/riscv_aplic.c +++ b/h

[PATCH v1] hw/intc/riscv_aplic: Remove redundant masking of hart_idx in riscv_aplic_msi_send()

The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed because the same operation is performed later in the address calculation. This change improves code clarity and avoids unnecessary operations. Signed-off-by: Huang Borong --- hw/intc/riscv_aplic.c | 1 - 1 f

[PATCH] hw/intc/riscv_aplic: Remove redundant masking of hart_idx in riscv_aplic_msi_send()

The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed because the same operation is performed later in the address calculation. This change improves code clarity and avoids unnecessary operations. Signed-off-by: Huang Borong --- hw/intc/riscv_aplic.c | 1 - 1 f