On Mon, Feb 6, 2023 at 3:34 PM Hao Wu wrote:
>
> Havard is no longer working on the Nuvoton systems for a while
> and won't be able to do any work on it in the future. So I'll
> take over maintaining the Nuvoton system from him.
>
> Signed-off-by: Hao Wu
Acked-by:
ive_get_next(), but with a helper function. Change it to use
> drive_get() directly. This makes the unit numbers explicit in the
> code.
>
> Cc: Havard Skinnemoen
> Cc: Tyrone Ting
> Cc: Peter Maydell
> Cc: qemu-...@nongnu.org
> Signed-off-by: Markus Armbruster
> ---
>
>> > This patch makes NPCM7XX Timer to use a the timer clock generated by the
> >> > CLK module instead of the magic number TIMER_REF_HZ.
> >> >
> >> > Reviewed-by: Havard Skinnemoen
> >> > Reviewed-by: Tyrone Ting
> >> > Signed-o
alse.
>
> This fixes some Coverity issues where Coverity knows that
> g_assert_true() can continue when the condition is false and
> complains about the possible array overrun at various callsites.
>
> Fixes: Coverity CID 1442340, 1442341, 1442343, 1442344, 1442345, 1442346
> Signed-off-by: Peter Maydell
Reviewed-by: Havard Skinnemoen
et_duty ../tests/qtest/npcm7xx_pwm-test.c:210
> > #17 0x5563130c7529 in test_toggle ../tests/qtest/npcm7xx_pwm-test.c:447
> >
> > Reported-by: Euler Robot
> > Signed-off-by: Gan Qixin
> > ---
> > Cc: Havard Skinnemoen
> > Cc: Tyrone Ting
> > Cc: Thomas Huth
> > Cc: Laurent Vivier
> > ---
> > tests/qtest/npcm7xx_pwm-test.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
>
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Havard Skinnemoen
Thanks!
Hi Bin,
On Thu, Jan 14, 2021 at 6:08 PM Bin Meng wrote:
>
> Hi Francisco,
>
> On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > The m25p80 model uses s->needed_bytes to indicate how
On Thu, Jan 14, 2021 at 7:10 AM Bin Meng wrote:
>
> From: Bin Meng
>
> I believe send_dummy_bits() should also be fixed, but I really don't
> know how based on my pure read/guess of the codes since there is no
> public datasheet available for this NPCM7xx SoC.
>
> Signed-off-by: Bin Meng
Just a
On Fri, Dec 11, 2020 at 4:16 PM Corey Minyard wrote:
> On Fri, Dec 11, 2020 at 12:56:07PM -0800, Hao Wu wrote:
> > Tl,dr: We'll remove the IPMI changes from the current patch set and
> > refactor
> > them in a separate patch set.
> >
> > Thank you for your review! On high level, we are
aybe-uninitialized]
>28 | g_free (*pp);
> | ^~~~
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
Reviewed-by: Havard Skinnemoen
I'd be totally fine with Philippe's suggestion too.
Thanks!
> ---
> tests/qtest/npcm7xx_timer-test.c |
og_action
> ../tests/qtest/npcm7xx_watchdog_timer-test.c:94
> #13 0x556487d25765 in test_enabling_flags
> ../tests/qtest/npcm7xx_watchdog_timer-test.c:243
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
Reviewed-by: Havard Skinnemoen
> ---
> tests/qtest/npcm
Dump the collected random data after a randomness test failure.
Note that you won't actually see this unless you add
g_test_set_nonfatal_assertions() back in.
Signed-off-by: Havard Skinnemoen
---
tests/qtest/npcm7xx_rng-test.c | 12
1 file changed, 12 insertions(+)
diff --
Even though g_test_set_nonfatal_assertions() makes test failure
reporting a lot better, no other tests currently do this so we'll turn
it off as well.
Signed-off-by: Havard Skinnemoen
---
tests/qtest/npcm7xx_gpio-test.c | 1 -
tests/qtest/npcm7xx_rng-test.c| 1 -
make sense to apply all three, but I'd definitely take (1), and I'll
leave it up to you whether to apply (2), (3) or both.
Havard Skinnemoen (3):
tests/qtest/npcm7xx_rng-test: count runs properly
tests/qtest/npcm7xx: Don't call g_test_set_nonfatal_assertions
tests/qtest/npcm7xx
ff-by: Havard Skinnemoen
---
tests/qtest/npcm7xx_rng-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
index da6e639bf6..57787c5ffc 100644
--- a/tests/qtest/npcm7xx_rng-test.c
+++ b/tests/qtest/npcm7xx_rng-t
On Mon, Nov 2, 2020 at 9:14 AM Peter Maydell wrote:
>
> On Mon, 2 Nov 2020 at 16:50, Havard Skinnemoen wrote:
> > But none of this is really specific to the RNG test, so I can remove
> > it if you prefer for consistency.
>
> I would prefer us to be consistent. If you want
On Mon, Nov 2, 2020 at 3:36 AM Peter Maydell wrote:
>
> On Fri, 23 Oct 2020 at 22:06, Havard Skinnemoen
> wrote:
> >
> > The RNG module returns a byte of randomness when the Data Valid bit is
> > set.
> >
> > This implementation ignores the prescaler setti
v("QEMU_TEST_FLAKY_RNG_TESTS")) {
> +qtest_add_func("npcm7xx_rng/continuous/monobit",
> test_continuous_monobit);
> +qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
> +qtest_add_func("npcm7xx_rng/first_byte/monobit",
> test_first_byte_monobit);
> +qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
> +}
Reviewed-by: Havard Skinnemoen
Thanks!
> qtest_start("-machine npcm750-evb");
> ret = g_test_run();
> --
> 2.20.1
>
On Fri, Oct 30, 2020 at 6:34 AM Peter Maydell wrote:
>
> On Fri, 23 Oct 2020 at 22:06, Havard Skinnemoen
> wrote:
> >
> > The RNG module returns a byte of randomness when the Data Valid bit is
> > set.
> >
> > This implementation ignores the prescaler
for driving the pin externally.
Like the nRF51 GPIO controller, a gpio level may be negative, which
means the pin is not driven, or floating.
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 2 +-
include/hw/arm/npcm7xx.h| 2 +
include
d-off-by: Hao Wu
Signed-off-by: Havard Skinnemoen
---
include/hw/misc/npcm7xx_clk.h | 2 +
include/hw/timer/npcm7xx_timer.h | 48 +++-
hw/arm/npcm7xx.c | 12 +
hw/misc/npcm7xx_clk.c | 28 ++
hw/timer/npcm7xx_ti
ion=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting
Reviewed-by: Gerd Hoffmann
Signed-off-by: H
timer: Adding watchdog for NPCM7XX Timer.
Havard Skinnemoen (5):
tests/qtest: Make npcm7xx_timer-test conditional on CONFIG_NPCM7XX
Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause
hw/misc: Add npcm7xx random number generator
hw/arm/npcm7xx: Add EHCI and OHCI controllers
hw/gpio
included.
Reviewed-by: Tyrone Ting
Reviewed-by: Peter Maydell
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst| 2 +-
include/hw/arm/npcm7xx.h | 2 +
include/hw/misc/npcm7xx_rng.h | 34
hw/arm/npcm7xx.c | 7 +-
hw/misc/npcm7xx_rng.c | 180
This test won't work if qemu was compiled without CONFIG_NPCM7XX, as
pointed out by Thomas Huth on a different patch.
Signed-off-by: Havard Skinnemoen
---
tests/qtest/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/meson.build b/tests/
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/timer/npcm7xx_timer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
Public bug reported:
Steps to reproduce:
1. Add a new device along with a qtest to exercise it.
2. Run make check-qtest. It passes.
3. Revert the commit that added the device and qtest.
4. Run make check-qtest again. It now fails because the device no longer
exists, but the test is somehow still
ion=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting
Reviewed-by: Gerd Hoffmann
Signed-off-by: H
for driving the pin externally.
Like the nRF51 GPIO controller, a gpio level may be negative, which
means the pin is not driven, or floating.
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 2 +-
include/hw/arm/npcm7xx.h| 2 +
include
included.
Reviewed-by: Tyrone Ting
Reviewed-by: Peter Maydell
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst| 2 +-
include/hw/arm/npcm7xx.h | 2 +
include/hw/misc/npcm7xx_rng.h | 34
hw/arm/npcm7xx.c | 7 +-
hw/misc/npcm7xx_rng.c | 180
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/timer/npcm7xx_timer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
d-off-by: Hao Wu
Signed-off-by: Havard Skinnemoen
---
include/hw/misc/npcm7xx_clk.h | 2 +
include/hw/timer/npcm7xx_timer.h | 48 +++-
hw/arm/npcm7xx.c | 12 +
hw/misc/npcm7xx_clk.c | 28 ++
hw/timer/npcm7xx_ti
avard
Hao Wu (1):
hw/timer: Adding watchdog for NPCM7XX Timer.
Havard Skinnemoen (4):
Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause
hw/misc: Add npcm7xx random number generator
hw/arm/npcm7xx: Add EHCI and OHCI controllers
hw/gpio: Add GPIO model for Nuvoton NPCM7xx
On Tue, Oct 20, 2020 at 6:02 AM Peter Maydell wrote:
>
> On Fri, 9 Oct 2020 at 00:22, Havard Skinnemoen wrote:
> >
> > The RNG module returns a byte of randomness when the Data Valid bit is
> > set.
> >
> > This implementation ignores the prescaler setting,
for driving the pin externally.
Like the nRF51 GPIO controller, a gpio level may be negative, which
means the pin is not driven, or floating.
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 2 +-
include/hw/arm/npcm7xx.h| 2 +
include
ion=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Cc: Gerd Hoffmann
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinn
This allows us to reuse npcm7xx_timer_pause for the watchdog timer.
Signed-off-by: Havard Skinnemoen
---
hw/timer/npcm7xx_timer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index 5703e43d40..2df9e3e496 100644
included.
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst| 2 +-
include/hw/arm/npcm7xx.h | 2 +
include/hw/misc/npcm7xx_rng.h | 34
hw/arm/npcm7xx.c | 7 +-
hw/misc/npcm7xx_rng.c | 179 +
tests
exercises all the timers in all the timer modules, which
expands to 180 test cases in total.
Reviewed-by: Tyrone Ting
Signed-off-by: Havard Skinnemoen
---
tests/qtest/npcm7xx_timer-test.c | 562 +++
tests/qtest/meson.build | 1 +
2 files changed, 563 insertions
d-off-by: Hao Wu
Signed-off-by: Havard Skinnemoen
---
include/hw/misc/npcm7xx_clk.h | 9 +
include/hw/timer/npcm7xx_timer.h | 43 ++-
hw/arm/npcm7xx.c | 11 +
hw/misc/npcm7xx_clk.c | 20 ++
hw/timer/npcm7xx_ti
https://github.com/hskinnemoen/qemu
Again, thanks a lot for reviewing!
Havard
Hao Wu (1):
hw/timer: Adding watchdog for NPCM7XX Timer.
Havard Skinnemoen (5):
tests/qtest: Add npcm7xx timer test
Move npcm7xx_timer_reached_zero call out of npcm7xx_timer_pause
hw/misc: Add npcm7xx random
On Tue, Sep 29, 2020 at 10:46 AM Corey Minyard wrote:
>
> On Mon, Sep 28, 2020 at 05:39:13PM -0700, Havard Skinnemoen via wrote:
> > This series briefly documents the existing IPMI device support for main
> > processor emulation, and goes on to propose a similar device struct
On Mon, Sep 28, 2020 at 10:27 PM Cédric Le Goater wrote:
>
> On 9/29/20 2:39 AM, Havard Skinnemoen wrote:
> > This series briefly documents the existing IPMI device support for main
> > processor emulation, and goes on to propose a similar device structure to
> > emulate I
;make sphinxdocs" can be seen here:
https://hskinnemoen.github.io/qemu/specs/ipmi.html
Signed-off-by: Havard Skinnemoen
---
docs/specs/ipmi.rst | 83 +
1 file changed, 83 insertions(+)
diff --git a/docs/specs/ipmi.rst b/docs/specs/ipmi.rst
index
This document is an attempt to briefly document the existing IPMI
emulation support on the main processor. It provides the necessary
background for the BMC-side IPMI emulation proposed by the next patch.
Signed-off-by: Havard Skinnemoen
---
docs/specs/index.rst | 1 +
docs/specs/ipmi.rst
Signed-off-by: Havard Skinnemoen
---
docs/conf.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/docs/conf.py b/docs/conf.py
index 0dbd90dc11..7c72f1a074 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -67,7 +67,10 @@ needs_sphinx = '1.6'
# Add any Sphinx
my team mates on
implementing the common part, as well as the Nuvoton-specific responder device.
Possibly also an Aspeed device.
Havard Skinnemoen (3):
docs: enable sphinx blockdiag extension
docs/specs: IPMI device emulation: main processor
docs/specs: IPMI device emulation: BMC
docs/conf.p
to a parameter that cannot be negative.
> 221 npcm7xx_fiu_select(fiu, cs_id);
>
> Since the index of the flash can not be negative, return an
> unsigned type.
>
> Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS)
> Signed-off-by: Philippe Mathieu-Da
On Fri, Sep 18, 2020 at 6:57 AM Philippe Mathieu-Daudé
wrote:
>
> On Fri, Sep 18, 2020 at 3:52 PM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Havard,
> >
> > On Mon, Sep 14, 2020 at 5:47 PM Peter Maydell
> > wrote:
> > >
> > > From: Hava
run it by default.
> The test can still be run setting the AVOCADO_TIMEOUT_EXPECTED
> environment variable.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Havard Skinnemoen
Tested-by: Havard Skinnemoen
Thanks!
> ---
> Supersedes: <20200918142344.15074
On Fri, Sep 18, 2020 at 7:27 AM Philippe Mathieu-Daudé wrote:
>
> On 9/18/20 4:23 PM, Philippe Mathieu-Daudé wrote:
> > The 'arm_quanta_gsj_initrd' test is timeouting on GitLab CI:
> > https://gitlab.com/philmd/qemu/-/jobs/745483978#L846
> >
> > Use the same trick from the 'arm_quanta_gsj' test to
On Fri, Sep 11, 2020 at 5:46 AM Philippe Mathieu-Daudé
wrote:
>
>
> On 9/11/20 7:20 AM, Havard Skinnemoen via wrote:
> > This allows these NPCM7xx-based boards to boot from a flash image, e.g.
> > one built with OpenBMC. For example like this:
> >
> > IMAGE=${OPE
kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
tests/acceptance/boot_linux_console.py
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx_boards.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
r not they're connected to actual flash chips.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 2 +
incl
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
---
include/hw
Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
---
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/npcm7xx.h| 19 +
hw/arm/npcm7xx_boards.c | 145
hw/arm/meson.build
Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx_boards.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 939391c3a3
).
We don't bother checking for PLL lock because we know our emulated PLLs
lock instantly.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 1 +
hw/arm/npcm7xx.c | 32 ++
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 92 +
docs/system/target-arm.rst | 1 +
2 files changed, 93 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
.
The chips themselves have a lot more features, some of which will be
added to the model at a later stage.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
Stanley
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/timer/npcm7xx_timer.h | 78 +
hw/timer/npcm7xx_timer.c | 543 +++
hw/timer/meson.build
This is a minimalistic boot ROM written specifically for use with QEMU.
It supports loading the second-stage loader from SPI flash into RAM, SMP
boot, and not much else.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
.gitmodules
the series with additional patches to enable booting from flash:
- Boot ROM (through the -bios option).
- OTP (fuse) controller.
- Memory Controller stub (just enough to skip memory training).
- Flash controller.
- Board-specific flash initialization.
Thanks for rev
made even though I don't think the kernel needs them.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
---
include/hw
and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.
Reviewed-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Tested-by: Alexander Bulekov
Signed-off-by: Havard Skinnemoen
On Tue, Sep 8, 2020 at 6:32 PM Havard Skinnemoen
wrote:
> On Tue, Sep 8, 2020 at 12:52 PM Havard Skinnemoen
> wrote:
> >
> > On Tue, Sep 8, 2020 at 9:58 AM Philippe Mathieu-Daudé
> wrote:
> > >
> > > On 9/8/20 5:52 PM, Philippe Mathieu-Daudé wrote:
>
On Thu, Sep 3, 2020 at 11:59 AM Philippe Mathieu-Daudé
wrote:
> On 8/25/20 2:17 AM, Havard Skinnemoen via wrote:
> > If a -bios option is specified on the command line, load the image into
> > the internal ROM memory region, which contains the first instructions
> > run b
On Tue, Sep 8, 2020 at 12:52 PM Havard Skinnemoen
wrote:
>
> On Tue, Sep 8, 2020 at 9:58 AM Philippe Mathieu-Daudé wrote:
> >
> > On 9/8/20 5:52 PM, Philippe Mathieu-Daudé wrote:
> > > On 9/8/20 5:02 PM, Alexander Bulekov wrote:
> > >> Hi Havard,
> >
>> failed: (t->remaining_ns > 0)
> >> Bail out! ERROR:../hw/timer/npcm7xx_timer.c:160:npcm7xx_timer_pause:
> >> assertion failed: (t->remaining_ns > 0)
> >> Aborted
> >>
> >> I'm doing the same for the quanta-gsj machine, b
On Mon, Sep 7, 2020 at 12:58 PM Alexander Bulekov wrote:
>
> On 200907 1547, Alexander Bulekov wrote:
> > On 200824 1717, Havard Skinnemoen via wrote:
> > > This supports reading and writing OTP fuses and keys. Only fuse reading
> > > has been tested.
On Mon, Sep 7, 2020 at 6:40 AM Philippe Mathieu-Daudé wrote:
>
> On 9/5/20 12:38 AM, Havard Skinnemoen wrote:
> > On Fri, Sep 4, 2020 at 3:02 PM Havard Skinnemoen
> > wrote:
> >>
> >> On Fri, Sep 4, 2020 at 2:32 AM Philippe Mathieu-Daudé
> >>
On Fri, Sep 4, 2020 at 3:02 PM Havard Skinnemoen wrote:
>
> On Fri, Sep 4, 2020 at 2:32 AM Philippe Mathieu-Daudé wrote:
> >
> > On 8/25/20 2:16 AM, Havard Skinnemoen via wrote:
> > > Enough functionality to boot the Linux kernel has been implemented. This
> > &g
On Fri, Sep 4, 2020 at 2:32 AM Philippe Mathieu-Daudé wrote:
>
> On 8/25/20 2:16 AM, Havard Skinnemoen via wrote:
> > Enough functionality to boot the Linux kernel has been implemented. This
> > includes:
> >
> > - Correct power-on reset values so
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx_boards.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index b67e45e913..70e5c34216
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 3 +
include/hw/nvram/npcm7xx_otp.h
kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
tests/acceptance/boot_linux_console.py | 83 ++
1 file change
).
We don't bother checking for PLL lock because we know our emulated PLLs
lock instantly.
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 1 +
hw/arm/npcm7xx.c | 32
2 files changed, 33 insertions(+)
diff --git a/include/hw/arm/npcm7x
This is a minimalistic boot ROM written specifically for use with QEMU.
It supports loading the second-stage loader from SPI flash into RAM, SMP
boot, and not much else.
Signed-off-by: Havard Skinnemoen
---
Makefile| 1 +
.gitmodules | 3 +++
MAINTAINERS
Le Goater
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx_boards.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 0b9dce2b35..b67e45e913 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm
.
The chips themselves have a lot more features, some of which will be
added to the model at a later stage.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 85
hw/arm/npcm7xx.c
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 90 +
docs/system/target-arm.rst | 1 +
2 files changed, 91 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
diff --git a/docs/system/arm
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h| 2 +
include/hw/mem/npcm7xx_mc.h | 36
Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/npcm7xx.h| 19 +
hw/arm/npcm7xx_boards.c | 144
hw/arm/meson.build | 2 +-
4 files changed, 165 insertions(+), 1 deletion
made even though I don't think the kernel needs them.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
include/hw/misc/npcm7xx_clk.h | 48 ++
hw/misc/npcm7xx_clk.c | 266 ++
hw
r not they're connected to actual flash chips.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 2 +
include/hw/ssi/npcm7xx_fiu.h | 73 +
hw/arm/npcm7xx.c | 58 ++
and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.
Reviewed-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/misc/npcm7xx_gcr.h | 43 ++
hw/misc/npcm7xx_gcr.c
Stanley
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/timer/npcm7xx_timer.h | 78 +
hw/timer/npcm7xx_timer.c | 509 +++
hw/timer/meson.build | 1 +
hw/timer/trace-events| 5 +
4 files changed
ng from flash:
- Boot ROM (through the -bios option).
- OTP (fuse) controller.
- Memory Controller stub (just enough to skip memory training).
- Flash controller.
- Board-specific flash initialization.
Thanks for reviewing,
Havard
Havard Skinnemoen (14):
hw/misc: Add NPCM7
On Thu, Aug 20, 2020 at 10:46 AM Philippe Mathieu-Daudé wrote:
>
> On 8/20/20 6:24 PM, Havard Skinnemoen wrote:
> > On Wed, Aug 19, 2020 at 10:29 PM Philippe Mathieu-Daudé
> > wrote:
> >>
> >> +Eric / Richard for compiler optimizations.
> >>
>
On Wed, Aug 19, 2020 at 10:29 PM Philippe Mathieu-Daudé wrote:
>
> +Eric / Richard for compiler optimizations.
>
> On 8/20/20 3:53 AM, Havard Skinnemoen wrote:
> > On Tue, Aug 11, 2020 at 8:26 PM Havard Skinnemoen
> > wrote:
> >>
> >> On Tue, Aug
On Tue, Aug 11, 2020 at 8:26 PM Havard Skinnemoen
wrote:
>
> On Tue, Aug 11, 2020 at 1:48 AM Philippe Mathieu-Daudé
> wrote:
> > INTERRUPTED: Test interrupted by SIGTERM
> > Runner error occurred: Timeout reached
> > (240.45 s)
> >
> > Is that expected?
&g
On Tue, Aug 11, 2020 at 1:48 AM Philippe Mathieu-Daudé wrote:
>
> Hi Havard,
>
> On 8/11/20 2:46 AM, Havard Skinnemoen wrote:
> > This adds two acceptance tests for the quanta-gsj machine.
> >
> > One test downloads a lightly patched openbmc flash image from github
kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
tests/acceptance/boot_linux_console.py | 65 ++
1 file change
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 90 +
docs/system/target-arm.rst | 1 +
2 files changed, 91 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
diff --git a/docs/system/arm
r not they're connected to actual flash chips.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/Kconfig | 1 +
hw/arm/npcm7xx.c | 58
hw/ssi/Makefile.objs | 1
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx.c | 29 +++
hw/nvram/Makefile.objs
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx.c| 6 +++
hw/mem/Makefile.objs| 1
Le Goater
Signed-off-by: Havard Skinnemoen
---
hw/arm/npcm7xx_boards.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 0b9dce2b35..26ea97072b 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm
.
The chips themselves have a lot more features, some of which will be
added to the model at a later stage.
Reviewed-by: Tyrone Ting
Reviewed-by: Joel Stanley
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
hw/arm/Kconfig | 5 +
hw/arm/Makefile.objs
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