more often
> > than we need to.
> >
> > Correct the condition to test against tx_buffer_size, which is
> > where we track how big the allocated buffer is.
> >
> > Signed-off-by: Peter Maydell
> > ---
> > hw/net/npcm_gmac.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Philippe Mathieu-Daudé
>
> Reviewed-by: Hao Wu
PCM8XX PSPI driver probed successfully from dmesg log.
> >
> > Signed-off-by: Tim Lee
> > ---
> > hw/arm/npcm8xx.c | 11 ++-
> > include/hw/arm/npcm8xx.h | 2 ++
> > 2 files changed, 12 insertions(+), 1 deletion(-)
>
> Reviewed-by: Philippe Mathieu-Daudé
>
Reviewed-by: Hao Wu < wuhao...@google.com>
/20250224205053.104959-1-
> pierrick.bouv...@linaro.org/T/#u
>
> You're welcome to review it, or fix the problem differently if there is
> a better approach.
>
> Regards,
> Pierrick
>
> On 2/19/25 10:45, Hao Wu wrote:
> > These 2 values are different between NPCM7X
l 6 SIGABRT
>
> check-functional:
> 22/203 qemu:func-thorough+func-arm-thorough+thorough /
> func-arm-arm_quanta_gsj ERROR 0.79s exit
> status 1
> 38/203 qemu:func-quick+func-aarch64 / func-aarch64-migration
> ERROR
Thank you very much!
On Thu, Feb 20, 2025 at 8:18 AM Peter Maydell
wrote:
> On Wed, 19 Feb 2025 at 18:46, Hao Wu wrote:
> >
> > Changes since v4:
> >
> > 1. Bump vmstate versions on NPCM CLK and GCR modules.
> > 2. Remove "hw/boards.h" include in np
point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 117 +++--
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 119 inser
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 18 --
hw/misc/npcm_gcr.c | 2 ++
include/hw/misc
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daude
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 16
e
above to login prompt.
Hao Wu (17):
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw/misc: Move NPCM7XX GCR to NPCM GCR
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
hw
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewed-by:
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 805
include/hw
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
docs/system/arm/nuvoton.rst
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 253 +++
include/hw/arm/npcm8xx.h | 21
3 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
Reviewed-by: Philippe Mathieu-Daude
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 ->
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 133 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 5 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index d89e8c2c3b..ac22fb08cb
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 27 ---
include/hw/misc/npcm_gcr.h | 13 +++--
2
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/
-nuvoton/meta-evb-npcm845
The patch set can boot the evaluation board image built from the source
above to login prompt.
Hao Wu (17):
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 27
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 27 ---
include/hw/misc/npcm_gcr.h | 13 +++--
2
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 18 --
hw/misc/npcm_gcr.c | 2 ++
include/hw/misc
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 804
include/hw/arm/npcm8xx.h
point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 113 +++--
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 117 inser
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 129 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 132 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index d89e8c2c3b..fe6e332de7
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewed-by:
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 253 +++
include/hw/arm/npcm8xx.h | 21
3 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 16 ++--
include/hw/ssi
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 ->
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 11 +++
include/hw/ssi/npcm7xx_fiu.h
point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 113 -
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 120 inser
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 19 +--
include/hw/misc/npcm_clk.h | 9 -
2 files changed
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 253 +++
include/hw/arm/npcm8xx.h | 20
3 files changed, 274 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 27
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6
npcm845-evb.
The OpenBMC for NPCM845 evaluation board can be found at:
https://github.com/Nuvoton-Israel/openbmc/tree/npcm-v2.10/meta-evb/meta-evb-nuvoton/meta-evb-npcm845
The patch set can boot the evaluation board image built from the source
above to login prompt.
Hao Wu (17):
roms: Update vbootrom
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 804
include/hw/arm/npcm8xx.h
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 ->
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 26 +-
include/hw/misc/npcm_gcr.h | 13 +++--
2
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 131 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 7edad9e7d7..19a4b2cd17
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
Reviewed-by:
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README
On Tue, Jan 21, 2025 at 6:20 PM Alex Bennée wrote:
> Hao Wu writes:
>
> > Have you tried that the test can pass with this? If I remember
> correctly, interrupt won't trigger properly if not advancing the
> > timer
>
> Yes but the IRQ has yet to be enabled at th
On Tue, Jan 21, 2025 at 7:00 PM Titus Rwantare wrote:
> This has been useful when debugging and unsure if the guest is
> generating i2c traffic.
>
> Signed-off-by: Titus Rwantare
>
Reviewed-by: Hao Wu
> ---
> hw/misc/i2c-echo.c | 8
> hw/misc/trace-eve
Have you tried that the test can pass with this? If I remember correctly,
interrupt won't trigger properly if not advancing the timer
If the test passes it's probably fine to remove that.
On Mon, Jan 20, 2025 at 11:00 PM Alex Bennée wrote:
> Until there are timers enabled the semantics of clock
gt; to overflow because its operands are not cast to
>> a larger data type before performing arithmetic. Thus, need
>> to cast rpm to uint64_t.
>>
>> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>>
>> Signed-off-by: Tigran Sogomonian
>&g
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
roms/vboot
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 11 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 810
include/hw/arm/npcm8xx.h
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
---
h
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24 deletions(-)
diff --git a/hw
point.
Implementation of these clocks might be required when implementing
these modules.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/misc/npcm_clk.c | 113 -
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 120 insertions(+), 3 deletions(-)
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 17 +++--
include/hw/misc/npcm_clk.h | 9 -
2 files changed, 19 insertions(+), 7 deletions
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 256 +++
include/hw/arm/npcm8xx.h | 20 +++
3 files changed, 277 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
diff --git a/hw/arm/meson.build
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 131 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 295073ba14..52d0fa07ea 100644
--- a/hw/misc
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README | 8
pc-bios
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 24 +++-
include/hw/misc/npcm_gcr.h | 13 +++--
2 files changed, 26 insertions
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
roms/vboot
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_clk.c}
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 11 +++
include/hw/ssi/npcm7xx_fiu.h | 1 +
3 files changed, 14
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_gcr.c
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm
boot the evaluation board image built from the source
above to login prompt.
Hao Wu (17):
docs/system/arm: Add Description for NPCM8XX SoC
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
---
h
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README | 8
pc-bios
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 256 +++
include/hw/arm/npcm8xx.h | 20 +++
3 files changed, 277 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
diff --git a/hw/arm/meson.build
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 17 +++--
include/hw/misc/npcm_clk.h | 9 -
2 files changed, 19 insertions(+), 7 deletions
point.
Implementation of these clocks might be required when implementing
these modules.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/misc/npcm_clk.c | 113 -
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 120 insertions(+), 3 deletions(-)
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 131 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 295073ba14..52d0fa07ea 100644
--- a/hw/misc
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 11 +++
include/hw/ssi/npcm7xx_fiu.h | 1 +
3 files changed, 14
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_gcr.c
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 11 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 810
include/hw/arm/npcm8xx.h
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_clk.c}
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 24 +++-
include/hw/misc/npcm_gcr.h | 13 +++--
2 files changed, 26 insertions
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24 deletions(-)
diff --git a/hw
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm
evaluation board image built from the source
above to login prompt.
Hao Wu (17):
docs/system/arm: Add Description for NPCM8XX SoC
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw/misc: Move
On Mon, Oct 28, 2024 at 11:15 AM Patrick Leis wrote:
> Enable AT24C with ASPEED in the KConfig because the boards build this
> device.
>
> Signed-off-by: Patrick Leis
>
Reviewed-by: Hao Wu
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff -
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