TPM support, by using swtpm.
This looks sensible to me.
Reviewed-by: Graeme Gregory
Signed-off-by: Kun Qin
---
hw/arm/sbsa-ref.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index e720de306419..93eb3d1e363b 100644
--- a
On Wed, 31 May 2023, at 5:36 PM, Leif Lindholm wrote:
> On 2023-05-31 16:27, Peter Maydell wrote:
>> On Wed, 31 May 2023 at 15:58, Graeme Gregory wrote:
>>>> The current sbsa-ref cannot use EHCI controller which is only
>>>> able to do 32-bit DMA, since sb
On Wed, May 31, 2023 at 03:02:29PM +0800, wangyuquan1...@phytium.com.cn wrote:
> From: Yuquan Wang
>
> The current sbsa-ref cannot use EHCI controller which is only
> able to do 32-bit DMA, since sbsa-ref doesn't have RAM above 4GB.
> Hence, this uses XHCI to provide a usb controller with 64-bit
The other two
> are fine.
>
> Thanks,
>
I am happy with dropping the evb-proto-bmc machine. We used that
internally before actual hardware was available.
Graeme
> C.
>
>
>
> >
> >
> > >
> > > Thanks,
> > >
> > >
On Wed, Jan 12, 2022 at 01:45:05PM +0100, Cédric Le Goater wrote:
> Hello Gregory,
>
> On 1/12/22 11:57, Graeme Gregory wrote:
> > On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
> > > This series of patch introduce a dummy implemenation of aspeed i3c
> >
These patches arrived just in time for our i3c testing. This stops
our CI halting due to kernel panic on i3c probing.
Reviewed-by: Graeme Gregory
Tested-by: Graeme Gregory
> v3:
> - Remove unused AspeedI3CClass
> - Refine memory region
> - Refine register reset
> - Remove unr
been using a VM created using v4/v5 as my daily work machine
since v4 came out so.
Tested-by: Graeme Gregory
>
> Alex
>
> v1 -> v2:
>
> - New patch: hvf: Actually set SIG_IPI mask
> - New patch: hvf: Introduce hvf vcpu struct
> - New patch: hvf: arm: Mark CPU a
On Tue, Nov 03, 2020 at 10:47:10AM +, Alex Bennée wrote:
> We should at least document what this machine is about.
>
Looks good to me.
Reviewed-by: Graeme Gregory
> Cc: Graeme Gregory
> Cc: Leif Lindholm
> Cc: Hongbo Zhang
> Cc: Shashi Mallela
> Signe
On Thu, Oct 29, 2020 at 11:19:39AM +, Leif Lindholm wrote:
> Hi Peter, (+Ard)
>
> Graeme is on holiday this week, and I would like his input.
>
> On Wed, Oct 28, 2020 at 20:31:41 +, Peter Maydell wrote:
> > On Wed, 28 Oct 2020 at 08:59, Maxim Uvarov wrote:
> > >
> > > If we're emulating
On Thu, Oct 15, 2020 at 06:21:09PM +0300, Maxim Uvarov wrote:
> On Thu, 15 Oct 2020 at 17:12, Graeme Gregory wrote:
> >
> > On Wed, Oct 14, 2020 at 01:04:43PM -0400, Shashi Mallela wrote:
> > > This was added as a placeholder for the virt requirement suggested by
> >
-Shashi
>
> On Wed, 14 Oct 2020 at 05:31, Graeme Gregory <[1]gra...@nuviainc.com> wrote:
>
> On Tue, Oct 13, 2020 at 11:16:31AM -0400, Shashi Mallela wrote:
> > Included the newly implemented SBSA generic watchdog device model into
> > SBSA platform
>
On Tue, Oct 13, 2020 at 11:16:31AM -0400, Shashi Mallela wrote:
> Included the newly implemented SBSA generic watchdog device model into
> SBSA platform
>
> Signed-off-by: Shashi Mallela
> ---
> hw/arm/sbsa-ref.c | 50 +++
> 1 file changed, 50 insertio
On Wed, Oct 07, 2020 at 12:44:43PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/7/20 12:32 PM, Graeme Gregory wrote:
> > On Wed, Oct 07, 2020 at 12:24:32PM +0200, Philippe Mathieu-Daudé wrote:
> >> On 10/7/20 12:07 PM, Graeme Gregory wrote:
> >>> SMMUv3 has an erro
On Wed, Oct 07, 2020 at 12:24:32PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/7/20 12:07 PM, Graeme Gregory wrote:
> > SMMUv3 has an error in a previous patch where an i was transposed to a 1
> > meaning interrupts would not have been correctly assigned to the SMMUv3
> > ins
SMMUv3 has an error in a previous patch where an i was transposed to a 1
meaning interrupts would not have been correctly assigned to the SMMUv3
instance.
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the
machine state")
Signed-off-by: Graeme Gregory
---
h
ity
- added Reviewed-by
Graeme Gregory (2):
hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
hw/arm/sbsa-ref : allocate IRQs for SMMUv3
hw/arm/sbsa-ref.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--
2.25.1
ces part")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 65e64883b5..01863510d0 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -133,6 +133,7 @@ sta
On Sun, Oct 04, 2020 at 08:04:32PM +0200, Philippe Mathieu-Daudé wrote:
> There is a number of contributions from this domain,
> add its own entry to the gitdm domain map.
>
> Cc: Graeme Gregory
> Cc: Leif Lindholm
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-
SMMUv3 has an error in previous patch where a i was transposed to a 1
meaning interrupts would not have been correctly assigned to the SMMUv3
instance.
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the
machine state")
Signed-off-by: Graeme Gregory
---
hw/arm/
quot;)
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 47e83252c1..9109fb58be 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -138,6 +138,7 @@ static const int sb
Fix two issues with the smmuv3 initialisation, first where a previous
patch had transposed an i to a 1. The second an assumption that the
IRQs allocated were meant to be unique and not 0 based.
Graeme Gregory (2):
hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
hw/arm/sbsa-ref : allocate IRQs for
On Sat, Sep 26, 2020 at 09:45:24AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Gregory,
>
> On 9/25/20 4:00 PM, Auger Eric wrote:
> > Hi Gregory,
> >
> > On 9/25/20 3:39 PM, Graeme Gregory wrote:
> >> SMMUv3 has an error in previous patch where a i was trans
oving the gic in the
machine state")
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 257ada9425..9109fb58be 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -13
t; Sent from [1]Mailspring, the best free email app for work
> On Sep 17 2020, at 5:37 pm, Graeme Gregory wrote:
>
> Something still seems to have gone wrong with subject, and description
> of patch is missing? Missed blank line between 1st line and description?
>
&g
Something still seems to have gone wrong with subject, and description
of patch is missing? Missed blank line between 1st line and description?
Do you have the link to updated ACPI tables for testing out of interest?
On Thu, Sep 17, 2020 at 02:12:45PM -0400, Shashi Mallela wrote:
> Signed-off-by:
On Tue, Aug 25, 2020 at 05:52:17PM +0100, Leif Lindholm wrote:
> The sbsa-ref platform uses a minimal device tree to pass amount of memory
> as well as number of cpus to the firmware. However, when dumping that
> minimal dtb (with -M sbsa-virt,dumpdtb=), the resulting blob
> generates a warning whe
EC if we find other use cases in
future where ARM-TF and qemu need to communicate.
Signed-off-by: Graeme Gregory
---
hw/misc/meson.build | 2 +
hw/misc/sbsa_ec.c | 98 +
2 files changed, 100 insertions(+)
create mode 100644 hw/misc/sbsa_ec.c
diff
Add the previously created sbsa-ec device to the sbsa-ref machine in
secure memory so the PSCI implementation in ARM-TF can access it, but
not expose it to non secure firmware or OS except by via ARM-TF.
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 14 ++
1 file changed, 14
This series is to an add embedded controller to the sbsa-ref machine
so that PSCI can communicate platform power states to the platform
which in this case is QEMU.
v1->v2
- broke out the EC itself as hw/misc/sbsa_ec.c as seperate patch
- applied review comments to date
On Fri, Aug 21, 2020 at 03:49:11PM +0200, Philippe Mathieu-Daudé wrote:
> On 8/20/20 3:32 PM, Graeme Gregory wrote:
> > A difference between sbsa platform and the virt platform is PSCI is
> > handled by ARM-TF in the sbsa platform. This means that the PSCI code
> > there need
On Mon, Aug 24, 2020 at 03:59:38PM +0100, Peter Maydell wrote:
> On Thu, 20 Aug 2020 at 14:32, Graeme Gregory wrote:
> >
> > A difference between sbsa platform and the virt platform is PSCI is
> > handled by ARM-TF in the sbsa platform. This means that the PSCI code
> >
state")
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 570faac6e2..48c7cea291 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -565,7 +565,7 @@ static void create_p
EC if we find other use cases in
future where ARM-TF and qemu need to communicate.
Signed-off-by: Graeme Gregory
---
hw/arm/sbsa-ref.c | 95 +++
1 file changed, 95 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index f030a416fd
On Thu, Aug 20, 2020 at 02:32:01PM +0100, Graeme Gregory wrote:
> A difference between sbsa platform and the virt platform is PSCI is
> handled by ARM-TF in the sbsa platform. This means that the PSCI code
> there needs to communicate some of the platform power changes down
> to the q
On Tue, 3 Nov 2015, at 02:25 AM, Shannon Zhao wrote:
> Hi Graeme,
>
> On 2015/11/2 18:39, Graeme Gregory wrote:
> > According to ACPI specification 6.2.17 _CCA (Cache Coherency Attribute)
> > this attribute is compulsary on ARM systems. Add this attribute to
> > the P
: Graeme Gregory
---
hw/arm/virt-acpi-build.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 1aaff1f..1430125 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -180,6 +180,7 @@ static void acpi_dsdt_add_pci(Aml *scope
On Wed, Nov 12, 2014 at 11:07:22AM +, Mark Rutland wrote:
> [...]
>
> > > > > > We are currently suggesting adding an RDSP property to the chosen
> > > > > > node
> > > > > > in the tiny DT, but a command-line arguement like kexec proposed
> > > > > > could
> > > > > > be another option I gu
37 matches
Mail list logo
