I am using qemu 2.6.2 and i have the following option in my command line
"-device virtio-net-pci,netdev=net1,mac=XX:YY:XX:XX:99:99,id=n1". In the
realize function for virtio-net-pci the value of 'id' is not getting
reflected.
Is this a known issue or am i missing something ?
-Gaurav
Is it possible to generate a PCIe burst of greater than 2dw for any MMIO.
I see we have limit of max 2dw operation for any MemoryRegion defined by
the max access size.
--Thanks
I am using qemu 2.2.0 with e1000 as my default eth i/f. I want to trap data
packets from/to e1000 without using tap i/f.
Downstream packets i am able to get with 'e1000_send_packet'.
However, i am not able to inject packet back to the nic without tap. Can
someone point me to how can i do that ?
Hi Stefan,
I am working on something to move PCI devices to data plane architecture.
Do you know any know reasons, as to why this was not tried before ?
Regards,
On Fri, Jun 24, 2016 at 3:45 PM, Stefan Hajnoczi wrote:
> On Thu, Jun 23, 2016 at 08:56:34PM +0530, Gaurav Sharma wrote:
>
Hi,
I am trying to explore how the data plane mechanism works in QEMU. I
understand the behavior of QEMU big lock. Can someone clarify the following
w.r.t. to data plane :
1. Currently only virtio-blk-pci and virtio-scsi-pci have data plane
enabled ?
2. From qemu 2.1.0 data plane is enabled by de
In the command line, "-cpu $model,-$flag"? For example,
-cpu qemu64,-sse2
>> I have tried the same already. But my VM hangs if remove sse or sse2.
I am using qemu 2.2.0
On Tue, May 31, 2016 at 12:38 PM, Fam Zheng wrote:
> On Mon, 05/30 15:48, Gaurav Sharma wrote:
> &
I am trying to boot a 64 bit image using KVM. By default I understand
'qemu64' is the guest processor.
What I am trying is to not to expose certain features like sse, sse2 etc.
Even though the change the same in 'builtin_x86_defs' for qemu64, i still
see these features in the guest cpu ?
Am i missi
Hi was trying to do some digging for multi core scenarios both with and
without KVM.
In short i have some devices and a user application that does some r/w
operations on those devices.
As per my understanding, in case binary translation using TCG is invoked,
we only create a single Qemuthread for
Hi,
I am trying to understand how are interrupts handled in QEMU for ARM.
Currently, I am looking at how timer interrupts are handled and interfaced
to GIC, and how i sGOC than connected to the cpu.
During arm_cpu_initfn, we create timer objects :
cpu->gt_timer[PHYS/VIRT] = timer_new
1. How i
to be precise 'get_phys_addr_lpae' is the method where in mmu handling is
being done ?
Thanks,
On Tue, Dec 23, 2014 at 3:28 PM, Peter Maydell
wrote:
> On 23 December 2014 at 09:42, Gaurav Sharma
> wrote:
> > Do we have MPU/MMU support for aarch64 yet ?
> > For aar
Do we have MPU/MMU support for aarch64 yet ?
For aarch64, in 'aarch64_a57_initfn', I do not see the MPU feature being
enabled also, not same being handled in helper file.
Thanks,
Gaurav
Hi,
I just wanted to know if instruction fetch from non ram mapped region
supported in qemu ?
I looked at the code as how TLB is being formed and maintained, and my
understanding of the code confirms the same.
Just wanted to cross-check if that is correct ?
Thanks,
Gaurav
I was taking into consideration the behavior of afm, which it seems
suppresses write back.
However, i do get your point on this.
Regards,
Gaurav
On Thu, Nov 27, 2014 at 6:10 PM, Peter Maydell
wrote:
> On 27 November 2014 at 12:15, Gaurav Sharma
> wrote:
> > As per arm specs, if
As per arm specs, if the src and dest register are same, write back
operation is suppressed.
[Specs]
if memop == MemOp_LOAD && wback && n == t && n != 31 then
c = ConstrainUnpredictable();
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF,
Constraint_NOP};
case c of
when Cons
Hi,
I need some help regarding an issue I am facing.
I was trying some stuff by initializing a machine that I added using
machine_init. The corresponding file was added in the build infra and gets
compiled correctly.
However, i do not see the same getting initialized in the
register_module_init me
Hi,
After trying to re-base I see that the code implementation of
memory_region_init has been changed.
Initially it used to just set the various fields to some default value.
Now, it is trying to do a object initialize on the MemoryRegion object.
1. Where does this initialization happen in the cod
, Aug 22, 2014 at 7:58 PM, Peter Maydell
wrote:
> On 19 August 2014 13:39, Gaurav Sharma wrote:
> > I am running a simple bare metal program with only the above specified
> > instruction
> >
> > [Instrn]
> > fcvt h16 s25
> >
> > [register values]
infinity.
Thanks,
Gaurav
On Tue, Aug 19, 2014 at 2:42 AM, Peter Maydell
wrote:
> On 18 August 2014 22:04, Gaurav Sharma wrote:
> > Hi Peter,
> > I cross checked it with a AFM model, and the results are indeed
> different.
> > The problem I think lies in how we treat de-
rounding is set, we ignore and we return zero. This may
not be true and we may have a smallest possible denormalized number.
Thanks,
Gaurav
On Sun, Aug 17, 2014 at 1:14 AM, Peter Maydell
wrote:
> On 16 August 2014 20:06, Gaurav Sharma wrote:
> > Can some one confirm is th
Can some one confirm is this is an issue with qemu implementation ?
Thanks,
Gaurav
On Thu, Aug 14, 2014 at 1:07 PM, Gaurav Sharma
wrote:
> I am trying to execute a 'fcvt' instruction for conversion from single
> precision to half precision value.
> with the following v
I am trying to execute a 'fcvt' instruction for conversion from single
precision to half precision value.
with the following values :
[Instrn]
fcvt h16 s25
[register values]
SIMD register [25] = 0x9EA82A22AB98FBA8L
FPCR = 0x40ae2f54 [with according mask removing the UFE and other
unnecessary bit]
Hi,
While trying conversion of single precision float value to half precision
value for ARM, it seems the code generates incorrect values in some of the
scenarios :
"inline uint32_t perform_round16(iss_info *iss, uint32_t sign, int16_t exp,
uint32_t frac, FPRounding rounding)"
[Case 1]
1. From AR
.write(0xC2DC66415D15B180L)
X24.write(0x76b3630c86fae51f)
FPCR.write(0x5d931bb5)
FPSR.write(0x23c914ee)
I still need to confirm if its a issue.
Thanks,
Gaurav
On Fri, Aug 8, 2014 at 3:55 PM, Peter Maydell
wrote:
> On 8 August 2014 11:02, Gaurav Sharma wrote:
> > I am trying to
Hi,
I am trying to test the floating point instruction for arm in qemu.
For floating point reciprocal estimate instruction, for a64 i see a check
for underflow condition in float64 HELPER(recpe_f64) method :
" else if (f64_exp >= 1023 && fpst->flush_to_zero) "
1. how do we calculate the value to
Even in case of arm, the value returned in such cases is 0
Thanks,
Gaurav
On Wed, Jul 30, 2014 at 2:07 PM, Peter Maydell
wrote:
> On 30 July 2014 05:58, Gaurav Sharma wrote:
> > In the floating point conversion support , if the float value is NaN, I
> can
> > see that t
In the floating point conversion support , if the float value is NaN, I
can see that the largest integer value is returned.
1. Is this as per std ? In the IEEE 754 doc i could not find any statement
which says, about this.
Thanks,
Gaurav
After rebasing my code with the master branch, i have started getting error
for this method "curl_multi_socket_action".
In the file blocl/curl.c I can see function call for this method without
NEED_CURL_TIMER_CALLBACK directive check also.
Is this is know issue, and what i can do to get rid of it
Seems, I am bit confused. So if i have to dump the target cpu registers,
where would be the corresponding code to look into
On Tue, Apr 1, 2014 at 12:47 AM, Peter Maydell wrote:
> [put qemu-devel back on CC]
> On 31 March 2014 20:13, Gaurav Sharma wrote:
> > On Mon, Mar 31, 2014
I am trying to build a register trace for ARM target.
I am trying to just log the register values, for that I added TCG ops to
generate a helper function that dumps the register values in CPUARMState.
This helper function i have called at the end of disas_arm_state function,
so that if enabled i ge
I am trying to put a trace feature for ARM target which includes some
dissassembly and register value to be logged.
Is there any way i can get only the register values that have changed for
the executed instruction, rather than dumping the whole cpu state ?
Thanks,
Gaurav
lex Bennée wrote:
>
> Gaurav Sharma writes:
>
> > Hi,
> > I just wanted to know what is the current status armv8 support in qemu ?
> > After initial look into the source code i see the support for user mode.
> > Even though aarch64-softmmu is supported in the target li
Hi,
I just wanted to know what is the current status armv8 support in qemu ?
After initial look into the source code i see the support for user mode.
Even though aarch64-softmmu is supported in the target list, i do not see
any corresponding code for init in target-arm/cpu64.c.
Thanks,
Gaurav
wrote:
> On 26 February 2014 13:04, Gaurav Sharma wrote:
> > Hi,
> > I have been trying to trace the for how address translation is done for
> any
> > load/store instructions. I was trying to emulate arm on an x86-64
> machine.
> > However, i need some clarificati
Hi,
I have been trying to trace the for how address translation is done for any
load/store instructions. I was trying to emulate arm on an x86-64 machine.
However, i need some clarifications :
1. During the slow path, qemu uses helper functions to translate address.
2. This is done by calling the f
s this PC value a target virtual address or the host virtual address ?
How is the translation done ?
Thanks,
Gaurav
On Wed, Feb 12, 2014 at 1:17 PM, Gaurav Sharma wrote:
> Can anyone point it out to me where is the pc value translated from guest
> virtual address to host virtual address
Can anyone point it out to me where is the pc value translated from guest
virtual address to host virtual address ?
Thanks,
Gaurav
I know now as how the helper methods called for address translation.
In case of slow path, the address translation is done at the end of
block by method "tcg_out_tb_finalize". Any specific reasons for it ?
Thanks,
Gaurav
On 2/10/14, Gaurav Sharma wrote:
> Sorry if i am a bit slow
, Peter Maydell wrote:
> On 10 February 2014 09:46, Gaurav Sharma wrote:
>> I was able to trace the flow to some extent but i still have some queries
>> :
>> 1. CPUARCHState is the main structure where we store the register
>> info. for e.g. - CPUARMState for A
?
2. Where and when will the translation from guest virtual address to
host virtual address occur. For e.g. for a load instruction for arm
ldr r1, [r0] where will the address translation happen ?
On 2/8/14, Richard Henderson wrote:
> On 02/05/2014 11:22 PM, Gaurav Sharma wrote:
>> I
I am working on something where i need to use the primarily the TCG
part of qemu.
I am aware of the basic code flow for TB generation, execution etc.
What I am really looking is the entry / exit points for TCG and also
how the mapping of registers is done. I see there are many temporaries
created a
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